boards/bluepill/include/periph_conf.h File Reference

Peripheral MCU configuration for the bluepill board. More...

Detailed Description

#include "periph_cpu.h"
+ Include dependency graph for boards/bluepill/include/periph_conf.h:

Go to the source code of this file.

Macros

Clock settings
Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c
#define CLOCK_CORECLOCK   (72000000U)
 
#define CLOCK_HSE   (8000000U)
 
#define CLOCK_LSE   (1U)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 2)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_PLL_PREDIV   (1)
 
#define CLOCK_PLL_MUL   (9)
 
ADC configuration
#define ADC_CONFIG
 
#define ADC_NUMOF   10
 
I2C configuration
#define I2C_NUMOF   (2U)
 
#define I2C_0_EN   1
 
#define I2C_1_EN   0 /* Disabled by default since pins collide with USART3. */
 
#define I2C_IRQ_PRIO   1
 
#define I2C_APBCLK   (CLOCK_APB1)
 
#define I2C_0_DEV   I2C1
 
#define I2C_0_CLKEN()   (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
 
#define I2C_0_CLKDIS()   (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
 
#define I2C_0_EVT_IRQ   I2C1_EV_IRQn
 
#define I2C_0_EVT_ISR   isr_i2c1_ev
 
#define I2C_0_ERR_IRQ   I2C1_ER_IRQn
 
#define I2C_0_ERR_ISR   isr_i2c1_er
 
#define I2C_0_SCL_PIN   GPIO_PIN(PORT_B, 6)
 
#define I2C_0_SDA_PIN   GPIO_PIN(PORT_B, 7)
 
#define I2C_1_DEV   I2C2
 
#define I2C_1_CLKEN()   (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
 
#define I2C_1_CLKDIS()   (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
 
#define I2C_1_EVT_IRQ   I2C2_EV_IRQn
 
#define I2C_1_EVT_ISR   isr_i2c2_ev
 
#define I2C_1_ERR_IRQ   I2C2_ER_IRQn
 
#define I2C_1_ERR_ISR   isr_i2c2_er
 
#define I2C_1_SCL_PIN   GPIO_PIN(PORT_B, 10)
 
#define I2C_1_SDA_PIN   GPIO_PIN(PORT_B, 11)
 

Timer configuration

#define TIMER_0_ISR   isr_tim2
 
#define TIMER_1_ISR   isr_tim3
 
#define TIMER_2_ISR   isr_tim4
 
#define TIMER_NUMOF   (sizeof(timer_config) / sizeof(timer_config[0]))
 
static const timer_conf_t timer_config []
 

UART configuration

#define UART_0_ISR   (isr_usart1)
 
#define UART_1_ISR   (isr_usart2)
 
#define UART_2_ISR   (isr_usart3)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 
static const uart_conf_t uart_config []
 

PWM configuration

#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 
static const pwm_conf_t pwm_config []
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 

Macro Definition Documentation

◆ ADC_CONFIG

#define ADC_CONFIG
Value:
{ \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 0), .chan = 0 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 1), .chan = 1 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 2), .chan = 2 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 3), .chan = 3 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 4), .chan = 4 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 5), .chan = 5 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 6), .chan = 6 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 7), .chan = 7 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, \
{ .dev = 0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, \
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 66 of file boards/bluepill/include/periph_conf.h.

Variable Documentation

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_A, 8), .cc_chan = 0 },
{ .pin = GPIO_PIN(PORT_A, 9), .cc_chan = 1 },
{ .pin = GPIO_PIN(PORT_A, 10), .cc_chan = 2 },
{ .pin = GPIO_PIN(PORT_A, 11), .cc_chan = 3 } },
.af = GPIO_AF_OUT_PP,
.bus = APB2
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 194 of file boards/bluepill/include/periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 234 of file boards/bluepill/include/periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
6,
4,
2,
1
},
{
7,
7,
5,
3,
2
}
}

Definition at line 217 of file boards/bluepill/include/periph_conf.h.

◆ timer_config

const timer_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TIM2,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
},
{
.dev = TIM3,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.bus = APB1,
.irqn = TIM3_IRQn
},
{
.dev = TIM4,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM4EN,
.bus = APB1,
.irqn = TIM4_IRQn
}
}

Definition at line 86 of file boards/bluepill/include/periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.bus = APB2,
.irqn = USART1_IRQn
},
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_B, 11),
.tx_pin = GPIO_PIN(PORT_B, 10),
.bus = APB1,
.irqn = USART3_IRQn
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 121 of file boards/bluepill/include/periph_conf.h.