boards/feather-m0/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
62 #define CLOCK_USE_PLL (1)
63 
64 #if CLOCK_USE_PLL
65 /* edit these values to adjust the PLL output frequency */
66 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
67 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
68 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
69 #else
70 /* edit this value to your needs */
71 #define CLOCK_DIV (1U)
72 /* generate the actual core clock frequency */
73 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
74 #endif
75 
81 #define TIMER_NUMOF (2U)
82 #define TIMER_0_EN 1
83 #define TIMER_1_EN 1
84 
85 /* Timer 0 configuration */
86 #define TIMER_0_DEV TC3->COUNT16
87 #define TIMER_0_CHANNELS 2
88 #define TIMER_0_MAX_VALUE (0xffff)
89 #define TIMER_0_ISR isr_tc3
90 
91 /* Timer 1 configuration */
92 #define TIMER_1_DEV TC4->COUNT32
93 #define TIMER_1_CHANNELS 2
94 #define TIMER_1_MAX_VALUE (0xffffffff)
95 #define TIMER_1_ISR isr_tc4
96 
102 static const uart_conf_t uart_config[] = {
103  {
104  .dev = &SERCOM0->USART,
105  .rx_pin = GPIO_PIN(PA, 11), /* RX pin */
106  .tx_pin = GPIO_PIN(PA, 10), /* TX pin */
107  .mux = GPIO_MUX_C,
108  .rx_pad = UART_PAD_RX_3,
109  .tx_pad = UART_PAD_TX_2,
110  .flags = UART_FLAG_NONE,
111  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
112  }
113 };
114 
115 /* interrupt function name mapping */
116 #define UART_0_ISR isr_sercom0
117 
118 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
119 
125 #define PWM_0_EN 1
126 #define PWM_1_EN 1
127 #define PWM_MAX_CHANNELS 2
128 /* for compatibility with test application */
129 #define PWM_0_CHANNELS PWM_MAX_CHANNELS
130 #define PWM_1_CHANNELS PWM_MAX_CHANNELS
131 
132 /* PWM device configuration */
133 static const pwm_conf_t pwm_config[] = {
134 #if PWM_0_EN
135  {TCC0, {
136  /* GPIO pin, MUX value, TCC channel */
137  { GPIO_UNDEF, (gpio_mux_t)0, 0 },
138  { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 }, /* ~9 */
139  }},
140 #endif
141 #if PWM_1_EN
142  {TCC2, {
143  /* GPIO pin, MUX value, TCC channel */
144  { GPIO_PIN(PA, 16), GPIO_MUX_E, 0 }, /* ~11 */
145  { GPIO_UNDEF, (gpio_mux_t)0, 1 },
146  }},
147 #endif
148 };
149 
150 /* number of devices that are actually defined */
151 #define PWM_NUMOF (2U)
152 
158 #define ADC_0_EN 1
159 #define ADC_MAX_CHANNELS 14
160 /* ADC 0 device configuration */
161 #define ADC_0_DEV ADC
162 #define ADC_0_IRQ ADC_IRQn
163 
164 /* ADC 0 Default values */
165 #define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
166 #define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
167 
168 #define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
169 #define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
170 #define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
171 
172 static const adc_conf_chan_t adc_channels[] = {
173  /* port, pin, muxpos */
174  { GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0 }, /* A0 */
175  { GPIO_PIN(PB, 8), ADC_INPUTCTRL_MUXPOS_PIN2 }, /* A1 */
176  { GPIO_PIN(PB, 9), ADC_INPUTCTRL_MUXPOS_PIN3 }, /* A2 */
177  { GPIO_PIN(PA, 4), ADC_INPUTCTRL_MUXPOS_PIN4 }, /* A3 */
178  { GPIO_PIN(PA, 5), ADC_INPUTCTRL_MUXPOS_PIN5 }, /* A4 */
179  { GPIO_PIN(PB, 2), ADC_INPUTCTRL_MUXPOS_PIN10 }, /* A5 */
180 };
181 
182 #define ADC_0_CHANNELS (6U)
183 #define ADC_NUMOF ADC_0_CHANNELS
184 
190 static const spi_conf_t spi_config[] = {
191  {
192  .dev = &SERCOM4->SPI,
193  .miso_pin = GPIO_PIN(PA, 12),
194  .mosi_pin = GPIO_PIN(PB, 10),
195  .clk_pin = GPIO_PIN(PB, 11),
196  .miso_mux = GPIO_MUX_D,
197  .mosi_mux = GPIO_MUX_D,
198  .clk_mux = GPIO_MUX_D,
199  .miso_pad = SPI_PAD_MISO_0,
200  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
201  }
202 };
203 
204 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
205 
211 #define I2C_NUMOF (1U)
212 #define I2C_0_EN 1
213 #define I2C_1_EN 0
214 #define I2C_2_EN 0
215 #define I2C_3_EN 0
216 #define I2C_IRQ_PRIO 1
217 
218 #define I2C_0_DEV SERCOM3->I2CM
219 #define I2C_0_IRQ SERCOM3_IRQn
220 #define I2C_0_ISR isr_sercom3
221 /* I2C 0 GCLK */
222 #define I2C_0_GCLK_ID SERCOM3_GCLK_ID_CORE
223 #define I2C_0_GCLK_ID_SLOW SERCOM3_GCLK_ID_SLOW
224 /* I2C 0 pin configuration */
225 #define I2C_0_SDA GPIO_PIN(PA, 22) /* SDA pin */
226 #define I2C_0_SCL GPIO_PIN(PA, 23) /* SCL pin */
227 #define I2C_0_MUX GPIO_MUX_C
228 
234 #define RTC_NUMOF (1U)
235 #define RTC_DEV RTC->MODE2
236 
242 #define RTT_NUMOF (1U)
243 #define RTT_DEV RTC->MODE0
244 #define RTT_IRQ RTC_IRQn
245 #define RTT_IRQ_PRIO 10
246 #define RTT_ISR isr_rtc
247 #define RTT_MAX_VALUE (0xffffffff)
248 #define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
249 #define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
250 
252 #ifdef __cplusplus
253 }
254 #endif
255 
256 #endif /* PERIPH_CONF_H */
257 
select peripheral function D
void * dev
UART, USART or LEUART device used.
select peripheral function E
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
ADC Channel Configuration.
PWM device configuration.
select peripheral function C
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
UART device configuration.
use pad 2 for MOSI, pad 3 for SCK
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
cc2538_ssi_t * dev
SSI device.