boards/frdm-k22f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
33 static const clock_config_t clock_config = {
34  /*
35  * This configuration results in the system running from the FLL output with
36  * the following clock frequencies:
37  * Core: 60 MHz
38  * Bus: 30 MHz
39  * Flex: 20 MHz
40  * Flash: 20 MHz
41  */
42  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
43  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
44  .default_mode = KINETIS_MCG_MODE_FEE,
45  /* The crystal connected to OSC0 is 8 MHz */
46  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
47  .fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
48  .oscsel = 0, /* Use OSC0 for external clock */
49  .clc = 0, /* External load caps on the FRDM-K22F board */
50  .fll_frdiv = 0b011, /* Divide by 256 */
51  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
52  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 60 MHz */
53  .pll_prdiv = 0b00011, /* Divide by 4 */
54  .pll_vdiv = 0b00110, /* Multiply by 30 => PLL freq = 60 MHz */
55  .enable_oscillator = true,
56  .select_fast_irc = true,
57  .enable_mcgirclk = false,
58 };
59 #define CLOCK_CORECLOCK (60000000ul)
60 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
61 
67 #define PIT_NUMOF (2U)
68 #define PIT_CONFIG { \
69  { \
70  .prescaler_ch = 0, \
71  .count_ch = 1, \
72  }, \
73  { \
74  .prescaler_ch = 2, \
75  .count_ch = 3, \
76  }, \
77 }
78 #define LPTMR_NUMOF (1U)
79 #define LPTMR_CONFIG { \
80  { \
81  .dev = LPTMR0, \
82  .irqn = LPTMR0_IRQn, \
83  } \
84 }
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_ISR_0 isr_pit1
89 #define PIT_ISR_1 isr_pit3
90 #define LPTMR_ISR_0 isr_lptmr0
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = UART1,
100  .freq = CLOCK_CORECLOCK,
101  .pin_rx = GPIO_PIN(PORT_E, 1),
102  .pin_tx = GPIO_PIN(PORT_E, 0),
103  .pcr_rx = PORT_PCR_MUX(3),
104  .pcr_tx = PORT_PCR_MUX(3),
105  .irqn = UART1_RX_TX_IRQn,
106  .scgc_addr = &SIM->SCGC4,
107  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
108  .mode = UART_MODE_8N1,
109  .type = KINETIS_UART,
110  },
111 };
112 
113 #define UART_0_ISR (isr_uart1_rx_tx)
114 
115 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
116 
122 static const adc_conf_t adc_config[] = {
123  /* dev, pin, channel */
124  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
125  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
126  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
127  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
128  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */
129  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */
130  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */
131  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */
132 };
133 
134 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
135 
141 static const pwm_conf_t pwm_config[] = {
142  {
143  .ftm = FTM0,
144  .chan = {
145  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
146  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
147  { .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
148  },
149  .chan_numof = 3,
150  .ftm_num = 0
151  }
152 };
153 
154 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
155 
168 static const uint32_t spi_clk_config[] = {
169  (
170  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
171  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
172  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
173  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
174  ),
175  (
176  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
177  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
178  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
179  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
180  ),
181  (
182  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
183  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
184  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
185  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
186  ),
187  (
188  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
189  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
190  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
191  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
192  ),
193  (
194  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
195  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
196  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
197  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
198  )
199 };
200 
201 static const spi_conf_t spi_config[] = {
202  {
203  .dev = SPI0,
204  .pin_miso = GPIO_PIN(PORT_D, 3),
205  .pin_mosi = GPIO_PIN(PORT_D, 2),
206  .pin_clk = GPIO_PIN(PORT_D, 1),
207  .pin_cs = {
208  GPIO_PIN(PORT_C, 4),
209  GPIO_PIN(PORT_D, 4),
210  GPIO_UNDEF,
211  GPIO_UNDEF,
212  GPIO_UNDEF
213  },
214  .pcr = GPIO_AF_2,
215  .simmask = SIM_SCGC6_SPI0_MASK
216  }
217 };
218 
219 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
220 
227 #define I2C_NUMOF (1U)
228 #define I2C_0_EN 1
229 /* Low (10 kHz): MUL = 2, SCL divider = 1536, total: 3072 */
230 #define KINETIS_I2C_F_ICR_LOW (0x36)
231 #define KINETIS_I2C_F_MULT_LOW (1)
232 /* Normal (100 kHz): MUL = 2, SCL divider = 160, total: 320 */
233 #define KINETIS_I2C_F_ICR_NORMAL (0x1D)
234 #define KINETIS_I2C_F_MULT_NORMAL (1)
235 /* Fast (400 kHz): MUL = 1, SCL divider = 80, total: 80 */
236 #define KINETIS_I2C_F_ICR_FAST (0x14)
237 #define KINETIS_I2C_F_MULT_FAST (0)
238 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 30, total: 30 */
239 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x05)
240 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
241 
242 /* I2C 0 device configuration */
243 #define I2C_0_DEV I2C0
244 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
245 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
246 #define I2C_0_IRQ I2C0_IRQn
247 #define I2C_0_IRQ_HANDLER isr_i2c0
248 /* I2C 0 pin configuration */
249 #define I2C_0_PORT PORTB
250 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
251 #define I2C_0_PIN_AF 2
252 #define I2C_0_SDA_PIN 3
253 #define I2C_0_SCL_PIN 2
254 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
255 
261 #define RTT_NUMOF (1U)
262 #define RTC_NUMOF (1U)
263 #define RTT_DEV RTC
264 #define RTT_IRQ RTC_IRQn
265 #define RTT_IRQ_PRIO 10
266 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
267 #define RTT_ISR isr_rtc
268 #define RTT_FREQUENCY (1)
269 #define RTT_MAX_VALUE (0xffffffff)
270 
272 #ifdef __cplusplus
273 }
274 #endif
275 
276 #endif /* PERIPH_CONF_H */
277 
void * dev
UART, USART or LEUART device used.
FTM_Type * ftm
used FTM
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
FLL Engaged External Mode.
Clock configuration for Kinetis CPUs.
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
cc2538_uart_t *const UART1
UART1 Instance.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.