boards/frdm-k22f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
33 static const clock_config_t clock_config = {
34  /*
35  * This configuration results in the system running from the FLL output with
36  * the following clock frequencies:
37  * Core: 60 MHz
38  * Bus: 30 MHz
39  * Flex: 20 MHz
40  * Flash: 20 MHz
41  */
42  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
43  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
44  .rtc_clc = 0, /* External load caps on the FRDM-K22F board */
45  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
46  .clock_flags =
50  0,
51  .default_mode = KINETIS_MCG_MODE_FEE,
52  /* The crystal connected to OSC0 is 8 MHz */
53  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
54  .osc_clc = 0, /* External load caps on the FRDM-K22F board */
55  .oscsel = MCG_C7_OSCSEL(0), /* Use OSC0 for external clock */
56  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
57  .fll_frdiv = MCG_C1_FRDIV(0b011), /* Divide by 256 */
58  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
59  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 60 MHz */
60  .pll_prdiv = MCG_C5_PRDIV0(0b00011), /* Divide by 4 */
61  .pll_vdiv = MCG_C6_VDIV0(0b00110), /* Multiply by 30 => PLL freq = 60 MHz */
62 };
63 #define CLOCK_CORECLOCK (60000000ul)
64 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
65 
71 #define PIT_NUMOF (2U)
72 #define PIT_CONFIG { \
73  { \
74  .prescaler_ch = 0, \
75  .count_ch = 1, \
76  }, \
77  { \
78  .prescaler_ch = 2, \
79  .count_ch = 3, \
80  }, \
81 }
82 #define LPTMR_NUMOF (1U)
83 #define LPTMR_CONFIG { \
84  { \
85  .dev = LPTMR0, \
86  .irqn = LPTMR0_IRQn, \
87  .src = 2, \
88  .base_freq = 32768u, \
89  }, \
90 }
91 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
92 
93 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
94 #define PIT_ISR_0 isr_pit1
95 #define PIT_ISR_1 isr_pit3
96 #define LPTMR_ISR_0 isr_lptmr0
97 
103 static const uart_conf_t uart_config[] = {
104  {
105  .dev = UART1,
106  .freq = CLOCK_CORECLOCK,
107  .pin_rx = GPIO_PIN(PORT_E, 1),
108  .pin_tx = GPIO_PIN(PORT_E, 0),
109  .pcr_rx = PORT_PCR_MUX(3),
110  .pcr_tx = PORT_PCR_MUX(3),
111  .irqn = UART1_RX_TX_IRQn,
112  .scgc_addr = &SIM->SCGC4,
113  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
114  .mode = UART_MODE_8N1,
115  .type = KINETIS_UART,
116  },
117 };
118 
119 #define UART_0_ISR (isr_uart1_rx_tx)
120 
121 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
122 
128 static const adc_conf_t adc_config[] = {
129  /* dev, pin, channel */
130  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
131  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
132  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
133  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
134  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */
135  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */
136  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */
137  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */
138 };
139 
140 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
141 /*
142  * K22F ADC reference settings:
143  * 0: VREFH/VREFL external pin pair
144  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
145  * 2-3: reserved
146  */
147 #define ADC_REF_SETTING 0
148 
154 static const pwm_conf_t pwm_config[] = {
155  {
156  .ftm = FTM0,
157  .chan = {
158  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
159  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
160  { .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
161  },
162  .chan_numof = 3,
163  .ftm_num = 0
164  }
165 };
166 
167 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
168 
181 static const uint32_t spi_clk_config[] = {
182  (
183  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
184  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
185  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
186  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
187  ),
188  (
189  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
190  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
191  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
192  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
193  ),
194  (
195  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
196  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
197  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
198  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
199  ),
200  (
201  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
202  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
203  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
204  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
205  ),
206  (
207  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
208  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
209  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
210  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
211  )
212 };
213 
214 static const spi_conf_t spi_config[] = {
215  {
216  .dev = SPI0,
217  .pin_miso = GPIO_PIN(PORT_D, 3),
218  .pin_mosi = GPIO_PIN(PORT_D, 2),
219  .pin_clk = GPIO_PIN(PORT_D, 1),
220  .pin_cs = {
221  GPIO_PIN(PORT_C, 4),
222  GPIO_PIN(PORT_D, 4),
223  GPIO_UNDEF,
224  GPIO_UNDEF,
225  GPIO_UNDEF
226  },
227  .pcr = GPIO_AF_2,
228  .simmask = SIM_SCGC6_SPI0_MASK
229  }
230 };
231 
232 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
233 
240 static const i2c_conf_t i2c_config[] = {
241  {
242  .i2c = I2C0,
243  .scl_pin = GPIO_PIN(PORT_B, 2),
244  .sda_pin = GPIO_PIN(PORT_B, 3),
245  .freq = CLOCK_BUSCLOCK,
246  .speed = I2C_SPEED_FAST,
247  .irqn = I2C0_IRQn,
248  .scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
249  .sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
250  },
251 };
252 #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
253 #define I2C_0_ISR (isr_i2c0)
254 #define I2C_1_ISR (isr_i2c1)
255 
257 #ifdef __cplusplus
258 }
259 #endif
260 
261 #endif /* PERIPH_CONF_H */
262 
fast mode: ~400kbit/s
cc2538_uart_t * dev
pointer to the used UART device
I2C configuration options.
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
SPI_Type * dev
SPI device to use.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
FLL Engaged External Mode.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
Clock configuration for Kinetis CPUs.
I2C_Type * i2c
Pointer to hardware module registers.
Turn on OSC0 oscillator.
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.