boards/frdm-k22f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
33 static const clock_config_t clock_config = {
34  /*
35  * This configuration results in the system running from the FLL output with
36  * the following clock frequencies:
37  * Core: 60 MHz
38  * Bus: 30 MHz
39  * Flex: 20 MHz
40  * Flash: 20 MHz
41  */
42  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
43  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
44  .rtc_clc = 0, /* External load caps on the FRDM-K22F board */
45  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
46  .clock_flags =
50  0,
51  .default_mode = KINETIS_MCG_MODE_FEE,
52  /* The crystal connected to OSC0 is 8 MHz */
53  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
54  .osc_clc = 0, /* External load caps on the FRDM-K22F board */
55  .oscsel = MCG_C7_OSCSEL(0), /* Use OSC0 for external clock */
56  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
57  .fll_frdiv = MCG_C1_FRDIV(0b011), /* Divide by 256 */
58  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
59  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 60 MHz */
60  .pll_prdiv = MCG_C5_PRDIV0(0b00011), /* Divide by 4 */
61  .pll_vdiv = MCG_C6_VDIV0(0b00110), /* Multiply by 30 => PLL freq = 60 MHz */
62 };
63 #define CLOCK_CORECLOCK (60000000ul)
64 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
65 
71 #define PIT_NUMOF (2U)
72 #define PIT_CONFIG { \
73  { \
74  .prescaler_ch = 0, \
75  .count_ch = 1, \
76  }, \
77  { \
78  .prescaler_ch = 2, \
79  .count_ch = 3, \
80  }, \
81 }
82 #define LPTMR_NUMOF (1U)
83 #define LPTMR_CONFIG { \
84  { \
85  .dev = LPTMR0, \
86  .irqn = LPTMR0_IRQn, \
87  } \
88 }
89 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
90 
91 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
92 #define PIT_ISR_0 isr_pit1
93 #define PIT_ISR_1 isr_pit3
94 #define LPTMR_ISR_0 isr_lptmr0
95 
101 static const uart_conf_t uart_config[] = {
102  {
103  .dev = UART1,
104  .freq = CLOCK_CORECLOCK,
105  .pin_rx = GPIO_PIN(PORT_E, 1),
106  .pin_tx = GPIO_PIN(PORT_E, 0),
107  .pcr_rx = PORT_PCR_MUX(3),
108  .pcr_tx = PORT_PCR_MUX(3),
109  .irqn = UART1_RX_TX_IRQn,
110  .scgc_addr = &SIM->SCGC4,
111  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
112  .mode = UART_MODE_8N1,
113  .type = KINETIS_UART,
114  },
115 };
116 
117 #define UART_0_ISR (isr_uart1_rx_tx)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const adc_conf_t adc_config[] = {
127  /* dev, pin, channel */
128  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
129  { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
130  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
131  { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
132  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */
133  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */
134  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */
135  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */
136 };
137 
138 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
139 /*
140  * K22F ADC reference settings:
141  * 0: VREFH/VREFL external pin pair
142  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
143  * 2-3: reserved
144  */
145 #define ADC_REF_SETTING 0
146 
152 static const pwm_conf_t pwm_config[] = {
153  {
154  .ftm = FTM0,
155  .chan = {
156  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
157  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
158  { .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
159  },
160  .chan_numof = 3,
161  .ftm_num = 0
162  }
163 };
164 
165 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
166 
179 static const uint32_t spi_clk_config[] = {
180  (
181  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
182  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
183  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
184  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
185  ),
186  (
187  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
188  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
189  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
190  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
191  ),
192  (
193  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
194  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
195  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
196  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
197  ),
198  (
199  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
200  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
201  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
202  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
203  ),
204  (
205  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
206  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
207  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
208  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
209  )
210 };
211 
212 static const spi_conf_t spi_config[] = {
213  {
214  .dev = SPI0,
215  .pin_miso = GPIO_PIN(PORT_D, 3),
216  .pin_mosi = GPIO_PIN(PORT_D, 2),
217  .pin_clk = GPIO_PIN(PORT_D, 1),
218  .pin_cs = {
219  GPIO_PIN(PORT_C, 4),
220  GPIO_PIN(PORT_D, 4),
221  GPIO_UNDEF,
222  GPIO_UNDEF,
223  GPIO_UNDEF
224  },
225  .pcr = GPIO_AF_2,
226  .simmask = SIM_SCGC6_SPI0_MASK
227  }
228 };
229 
230 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
231 
238 #define I2C_NUMOF (1U)
239 #define I2C_0_EN 1
240 /* Low (10 kHz): MUL = 2, SCL divider = 1536, total: 3072 */
241 #define KINETIS_I2C_F_ICR_LOW (0x36)
242 #define KINETIS_I2C_F_MULT_LOW (1)
243 /* Normal (100 kHz): MUL = 2, SCL divider = 160, total: 320 */
244 #define KINETIS_I2C_F_ICR_NORMAL (0x1D)
245 #define KINETIS_I2C_F_MULT_NORMAL (1)
246 /* Fast (400 kHz): MUL = 1, SCL divider = 80, total: 80 */
247 #define KINETIS_I2C_F_ICR_FAST (0x14)
248 #define KINETIS_I2C_F_MULT_FAST (0)
249 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 30, total: 30 */
250 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x05)
251 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
252 
253 /* I2C 0 device configuration */
254 #define I2C_0_DEV I2C0
255 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
256 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
257 #define I2C_0_IRQ I2C0_IRQn
258 #define I2C_0_IRQ_HANDLER isr_i2c0
259 /* I2C 0 pin configuration */
260 #define I2C_0_PORT PORTB
261 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
262 #define I2C_0_PIN_AF 2
263 #define I2C_0_SDA_PIN 3
264 #define I2C_0_SCL_PIN 2
265 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
266 
272 #define RTT_NUMOF (1U)
273 #define RTC_NUMOF (1U)
274 #define RTT_DEV RTC
275 #define RTT_IRQ RTC_IRQn
276 #define RTT_IRQ_PRIO 10
277 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
278 #define RTT_ISR isr_rtc
279 #define RTT_FREQUENCY (1)
280 #define RTT_MAX_VALUE (0xffffffff)
281 
283 #ifdef __cplusplus
284 }
285 #endif
286 
287 #endif /* PERIPH_CONF_H */
288 
cc2538_uart_t * dev
pointer to the used UART device
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
FLL Engaged External Mode.
Clock configuration for Kinetis CPUs.
Turn on OSC0 oscillator.
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.