boards/frdm-k64f/include/periph_conf.h File Reference
#include "periph_cpu.h"
+ Include dependency graph for boards/frdm-k64f/include/periph_conf.h:
+ This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Clock system configuration

#define CLOCK_CORECLOCK   (60000000ul)
 
#define CLOCK_BUSCLOCK   (CLOCK_CORECLOCK / 1)
 
static const clock_config_t clock_config
 

Timer configuration

#define PIT_NUMOF   (2U)
 
#define PIT_CONFIG
 
#define LPTMR_NUMOF   (0U)
 
#define LPTMR_CONFIG   {}
 
#define TIMER_NUMOF   ((PIT_NUMOF) + (LPTMR_NUMOF))
 
#define PIT_BASECLOCK   (CLOCK_BUSCLOCK)
 
#define PIT_ISR_0   isr_pit1
 
#define PIT_ISR_1   isr_pit3
 
#define LPTMR_ISR_0   isr_lptmr0
 

UART configuration

#define UART_0_ISR   (isr_uart0_rx_tx)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 
static const uart_conf_t uart_config []
 

ADC configuration

#define ADC_NUMOF   (sizeof(adc_config) / sizeof(adc_config[0]))
 
#define ADC_REF_SETTING   0
 
static const adc_conf_t adc_config []
 

PWM configuration

#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 
static const pwm_conf_t pwm_config []
 

SPI configuration

Clock configuration values based on the configured 30Mhz module clock.

Auto-generated by: cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c

#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 
static const uint32_t spi_clk_config []
 
static const spi_conf_t spi_config []
 

I2C configuration

#define I2C_NUMOF   (sizeof(i2c_config) / sizeof(i2c_config[0]))
 
#define I2C_0_ISR   (isr_i2c0)
 
#define I2C_1_ISR   (isr_i2c1)
 
static const i2c_conf_t i2c_config []
 

Macro Definition Documentation

◆ PIT_CONFIG

#define PIT_CONFIG
Value:
{ \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
{ \
.prescaler_ch = 2, \
.count_ch = 3, \
}, \
}

Definition at line 73 of file boards/frdm-k64f/include/periph_conf.h.

Variable Documentation

◆ adc_config

const adc_conf_t adc_config[]
static
Initial value:
= {
[ 0] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 12, .avg = ADC_AVG_MAX },
[ 1] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 13, .avg = ADC_AVG_MAX },
[ 2] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 10), .chan = 14, .avg = ADC_AVG_MAX },
[ 3] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 11), .chan = 15, .avg = ADC_AVG_MAX },
[ 4] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7, .avg = ADC_AVG_MAX },
[ 5] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6, .avg = ADC_AVG_MAX },
[ 6] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0, .avg = ADC_AVG_MAX },
[ 7] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19, .avg = ADC_AVG_MAX },
[ 8] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX },
[ 9] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0, .avg = ADC_AVG_MAX },
[10] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19, .avg = ADC_AVG_MAX },
[11] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX },
[12] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 1, .avg = ADC_AVG_MAX },
[13] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 20, .avg = ADC_AVG_MAX },
[14] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX },
[15] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 1, .avg = ADC_AVG_MAX },
[16] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 20, .avg = ADC_AVG_MAX },
[17] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX },
[18] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 26, .avg = ADC_AVG_NONE },
[19] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 27, .avg = ADC_AVG_MAX },
}
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
#define ADC_AVG_NONE
Disable hardware averaging.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 122 of file boards/frdm-k64f/include/periph_conf.h.

◆ clock_config

const clock_config_t clock_config
static
Initial value:
= {
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
.rtc_clc = 0,
.osc32ksel = SIM_SOPT1_OSC32KSEL(2),
.clock_flags =
0,
.default_mode = KINETIS_MCG_MODE_PEE,
.osc_clc = 0,
.oscsel = MCG_C7_OSCSEL(0),
.fcrdiv = MCG_SC_FCRDIV(0),
.fll_frdiv = MCG_C1_FRDIV(0b111),
.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464,
.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920,
.pll_prdiv = MCG_C5_PRDIV0(0b10011),
.pll_vdiv = MCG_C6_VDIV0(0b00000),
}
PLL Engaged External Mode.
Use the fast internal reference clock as MCGIRCLK signal.

Definition at line 34 of file boards/frdm-k64f/include/periph_conf.h.

◆ i2c_config

const i2c_conf_t i2c_config[]
static
Initial value:
= {
{
.i2c = I2C0,
.scl_pin = GPIO_PIN(PORT_E, 24),
.sda_pin = GPIO_PIN(PORT_E, 25),
.freq = CLOCK_BUSCLOCK,
.speed = I2C_SPEED_FAST,
.irqn = I2C0_IRQn,
.scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
.sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
},
}
fast mode: ~400kbit/s
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 252 of file boards/frdm-k64f/include/periph_conf.h.

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.ftm = FTM0,
.chan = {
{ .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
{ .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
{ .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
},
.chan_numof = 4,
.ftm_num = 0
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 165 of file boards/frdm-k64f/include/periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
}
}
use alternate function 2
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 226 of file boards/frdm-k64f/include/periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = UART0,
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_B, 16),
.pin_tx = GPIO_PIN(PORT_B, 17),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_UART,
},
}
8 data bits, no parity, 1 stop bit
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
Kinetis UART module type.

Definition at line 97 of file boards/frdm-k64f/include/periph_conf.h.