boards/frdm-k64f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C"
27 {
28 #endif
29 
34 static const clock_config_t clock_config = {
35  /*
36  * This configuration results in the system running from the PLL output with
37  * the following clock frequencies:
38  * Core: 60 MHz
39  * Bus: 60 MHz
40  * Flex: 20 MHz
41  * Flash: 20 MHz
42  */
43  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
44  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
45  .rtc_clc = 0, /* External load caps on board */
46  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
47  .clock_flags =
48  /* No OSC0_EN, use EXTAL directly without OSC0 */
51  0,
52  .default_mode = KINETIS_MCG_MODE_PEE,
53  /* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
55  .osc_clc = 0, /* External load caps on board */
56  .oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL for external clock */
57  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
58  .fll_frdiv = MCG_C1_FRDIV(0b111), /* Divide by 1536 => FLL input 32252 Hz */
59  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
60  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
61  .pll_prdiv = MCG_C5_PRDIV0(0b10011), /* Divide by 20 */
62  .pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 60 MHz */
63 };
64 #define CLOCK_CORECLOCK (60000000ul)
65 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
66 
72 #define PIT_NUMOF (2U)
73 #define PIT_CONFIG { \
74  { \
75  .prescaler_ch = 0, \
76  .count_ch = 1, \
77  }, \
78  { \
79  .prescaler_ch = 2, \
80  .count_ch = 3, \
81  }, \
82  }
83 #define LPTMR_NUMOF (0U)
84 #define LPTMR_CONFIG {}
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_ISR_0 isr_pit1
89 #define PIT_ISR_1 isr_pit3
90 #define LPTMR_ISR_0 isr_lptmr0
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = UART0,
100  .freq = CLOCK_CORECLOCK,
101  .pin_rx = GPIO_PIN(PORT_B, 16),
102  .pin_tx = GPIO_PIN(PORT_B, 17),
103  .pcr_rx = PORT_PCR_MUX(3),
104  .pcr_tx = PORT_PCR_MUX(3),
105  .irqn = UART0_RX_TX_IRQn,
106  .scgc_addr = &SIM->SCGC4,
107  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
108  .mode = UART_MODE_8N1,
109  .type = KINETIS_UART,
110  },
111 };
112 
113 #define UART_0_ISR (isr_uart0_rx_tx)
114 
115 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
116 
122 static const adc_conf_t adc_config[] = {
123  [ 0] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 12 }, /* PTB2 (Arduino A0) */
124  [ 1] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 13 }, /* PTB3 (Arduino A1) */
125  [ 2] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 10), .chan = 14 }, /* PTB10 (Arduino A2) */
126  [ 3] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 11), .chan = 15 }, /* PTB11 (Arduino A3) */
127  [ 4] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 }, /* PTC11 (Arduino A4) */
128  [ 5] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 }, /* PTC10 (Arduino A5) */
129  [ 6] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
130  [ 7] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
131  [ 8] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK) }, /* ADC0_DP0 - ADC0_DM0 */
132  [ 9] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
133  [10] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
134  [11] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK) }, /* ADC1_DP0 - ADC1_DM0 */
135  [12] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 1 }, /* ADC0_DP1 */
136  [13] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 20 }, /* ADC0_DM1 */
137  [14] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK) }, /* ADC0_DP1 - ADC0_DM1 */
138  [15] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 1 }, /* ADC1_DP1 */
139  [16] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 20 }, /* ADC1_DM1 */
140  [17] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK) }, /* ADC1_DP1 - ADC1_DM1 */
141  /* internal: temperature sensor */
142  /* The temperature sensor has a very high output impedance, it must not be
143  * sampled using hardware averaging, or the sampled values will be garbage */
144  [18] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 26 },
145  /* internal: band gap */
146  /* Note: the band gap buffer uses a bit of current and is turned off by default,
147  * Set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading or the input will be floating */
148  [19] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 27 },
149 };
150 
151 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
152 /*
153  * K64F ADC reference settings:
154  * 0: VREFH/VREFL external pin pair
155  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
156  * 2-3: reserved
157  */
158 #define ADC_REF_SETTING 0
159 
165 static const pwm_conf_t pwm_config[] = {
166  {
167  .ftm = FTM0,
168  .chan = {
169  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
170  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
171  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
172  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
173  },
174  .chan_numof = 4,
175  .ftm_num = 0
176  }
177 };
178 
179 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
180 
193 static const uint32_t spi_clk_config[] = {
194  (
195  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
196  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
197  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
198  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
199  ),
200  (
201  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
202  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
203  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
204  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
205  ),
206  (
207  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
208  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
209  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
210  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
211  ),
212  (
213  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
214  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
215  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
216  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
217  ),
218  (
219  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
220  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
221  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
222  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
223  )
224 };
225 
226 static const spi_conf_t spi_config[] = {
227  {
228  .dev = SPI0,
229  .pin_miso = GPIO_PIN(PORT_D, 3),
230  .pin_mosi = GPIO_PIN(PORT_D, 2),
231  .pin_clk = GPIO_PIN(PORT_D, 1),
232  .pin_cs = {
233  GPIO_PIN(PORT_D, 0),
234  GPIO_UNDEF,
235  GPIO_UNDEF,
236  GPIO_UNDEF,
237  GPIO_UNDEF
238  },
239  .pcr = GPIO_AF_2,
240  .simmask = SIM_SCGC6_SPI0_MASK
241  }
242 };
243 
244 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
245 
252 static const i2c_conf_t i2c_config[] = {
253  {
254  .i2c = I2C0,
255  .scl_pin = GPIO_PIN(PORT_E, 24),
256  .sda_pin = GPIO_PIN(PORT_E, 25),
257  .freq = CLOCK_BUSCLOCK,
258  .speed = I2C_SPEED_FAST,
259  .irqn = I2C0_IRQn,
260  .scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
261  .sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
262  },
263 };
264 #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
265 #define I2C_0_ISR (isr_i2c0)
266 #define I2C_1_ISR (isr_i2c1)
267 
269 #ifdef __cplusplus
270 }
271 #endif
272 
273 #endif /* PERIPH_CONF_H */
274 
fast mode: ~400kbit/s
cc2538_uart_t * dev
pointer to the used UART device
I2C configuration options.
PLL Engaged External Mode.
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
SPI_Type * dev
SPI device to use.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
Clock configuration for Kinetis CPUs.
I2C_Type * i2c
Pointer to hardware module registers.
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.