boards/mulle/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
37  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
38  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
39  * capacitance as well. */
40 /* Use the equation
41  * CL = (C1 * C2) / (C1 + C2) + Cstray
42  * with C1 == C2:
43  * C1 = 2 * (CL - Cstray)
44  */
45 /* enable 14pF load capacitor which will yield a crystal load capacitance of 12 pF */
46 #define RTC_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK)
47 
48 static const clock_config_t clock_config = {
49  /*
50  * This configuration results in the system running from the FLL output with
51  * the following clock frequencies:
52  * Core: 48 MHz
53  * Bus: 48 MHz
54  * Flex: 24 MHz
55  * Flash: 24 MHz
56  */
57  /* The board has a 16 MHz crystal, though it is not used in this configuration */
58  /* This configuration uses the RTC crystal to provide the base clock, it
59  * should have better accuracy than the internal slow clock, and lower power
60  * consumption than using the 16 MHz crystal and the OSC0 module */
61  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
62  SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
63  .rtc_clc = RTC_LOAD_CAP_BITS,
64  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
65  .clock_flags =
66  /* no OSC0_EN, the RTC module provides the clock input signal for the FLL */
69  0,
70  .default_mode = KINETIS_MCG_MODE_FEE,
71  .erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
72  /* 16 pF capacitors yield ca 10 pF load capacitance as required by the
73  * onboard xtal, not used when OSC0 is disabled */
74  .osc_clc = OSC_CR_SC16P_MASK,
75  .oscsel = MCG_C7_OSCSEL(1), /* Use RTC for external clock */
76  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
77  .fll_frdiv = MCG_C1_FRDIV(0b000), /* Divide by 1 => FLL input 32768 Hz */
78  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
79  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
80  /* PLL is unavailable when using a 32768 Hz source clock, so the
81  * configuration below can only be used if the above config is modified to
82  * use the 16 MHz crystal instead of the RTC. */
83  .pll_prdiv = MCG_C5_PRDIV0(0b00111), /* Divide by 8 */
84  .pll_vdiv = MCG_C6_VDIV0(0b01100), /* Multiply by 36 => PLL freq = 72 MHz */
85 };
86 #define CLOCK_CORECLOCK (48000000ul)
87 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
88 
94 #define PIT_NUMOF (2U)
95 #define PIT_CONFIG { \
96  { \
97  .prescaler_ch = 0, \
98  .count_ch = 1, \
99  }, \
100  { \
101  .prescaler_ch = 2, \
102  .count_ch = 3, \
103  }, \
104  }
105 #define LPTMR_NUMOF (1U)
106 #define LPTMR_CONFIG { \
107  { \
108  .dev = LPTMR0, \
109  .irqn = LPTMR0_IRQn, \
110  .src = 2, \
111  .base_freq = 32768u, \
112  } \
113  }
114 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
115 
116 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
117 #define PIT_ISR_0 isr_pit1
118 #define PIT_ISR_1 isr_pit3
119 #define LPTMR_ISR_0 isr_lptmr0
120 
127 static const uart_conf_t uart_config[] = {
128  {
129  .dev = UART0,
130  .freq = CLOCK_CORECLOCK,
131  .pin_rx = GPIO_PIN(PORT_A, 15),
132  .pin_tx = GPIO_PIN(PORT_A, 14),
133  .pcr_rx = PORT_PCR_MUX(3),
134  .pcr_tx = PORT_PCR_MUX(3),
135  .irqn = UART0_RX_TX_IRQn,
136  .scgc_addr = &SIM->SCGC4,
137  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
138  .mode = UART_MODE_8N1,
139  .type = KINETIS_UART,
140  },
141  {
142  .dev = UART1,
143  .freq = CLOCK_CORECLOCK,
144  .pin_rx = GPIO_PIN(PORT_C, 3),
145  .pin_tx = GPIO_PIN(PORT_C, 4),
146  .pcr_rx = PORT_PCR_MUX(3),
147  .pcr_tx = PORT_PCR_MUX(3),
148  .irqn = UART1_RX_TX_IRQn,
149  .scgc_addr = &SIM->SCGC4,
150  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
151  .mode = UART_MODE_8N1,
152  .type = KINETIS_UART,
153  },
154 };
155 
156 #define UART_0_ISR (isr_uart0_rx_tx)
157 #define UART_1_ISR (isr_uart1_rx_tx)
158 
159 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
160 
166 static const adc_conf_t adc_config[] = {
167  /* internal: temperature sensor */
168  [ 0] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 26 },
169  /* internal: band gap */
170  [ 1] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 27 },
171  /* internal: V_REFSH */
172  [ 2] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 29 },
173  /* internal: V_REFSL */
174  [ 3] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 30 },
175  /* internal: DAC0 module output level */
176  [ 4] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 23 },
177  /* internal: VREF module output level */
178  [ 5] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 18 },
179  /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
180  [ 6] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 0 },
181  /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
182  [ 7] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 19 },
183  /* expansion port PGA0_DP pin */
184  [ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 0 },
185  /* expansion port PGA0_DM pin */
186  [ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 19 },
187  /* expansion port PTA17 */
188  [10] = { .dev = ADC1, .pin = GPIO_PIN(PORT_A, 17), .chan = 17 },
189  /* expansion port PTB0 */
190  [11] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 },
191  /* expansion port PTC0 */
192  [12] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 0), .chan = 14 },
193  /* expansion port PTC8 */
194  [13] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 8), .chan = 4 },
195  /* expansion port PTC9 */
196  [14] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 9), .chan = 5 },
197  /* expansion port PTC10 */
198  [15] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 },
199  /* expansion port PTC11 */
200  [16] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 }
201 };
202 
203 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
204 /*
205  * K60D ADC reference settings:
206  * 0: VREFH/VREFL external pin pair
207  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
208  * 2-3: reserved
209  */
210 #define ADC_REF_SETTING 0
211 
217 static const dac_conf_t dac_config[] = {
218  {
219  .dev = DAC0,
220  .scgc_addr = &SIM->SCGC2,
221  .scgc_bit = SIM_SCGC2_DAC0_SHIFT
222  }
223 };
224 
225 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
226 
232 static const pwm_conf_t pwm_config[] = {
233  {
234  .ftm = FTM0,
235  .chan = {
236  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
237  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
238  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
239  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
240  },
241  .chan_numof = 2,
242  .ftm_num = 0
243  },
244  {
245  .ftm = FTM1,
246  .chan = {
247  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
248  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
249  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
250  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
251  },
252  .chan_numof = 2,
253  .ftm_num = 1
254  }
255 };
256 
257 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
258 
270 static const uint32_t spi_clk_config[] = {
271  (
272  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
273  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
274  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
275  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
276  ),
277  (
278  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
279  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
280  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
281  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
282  ),
283  (
284  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
285  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
286  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
287  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
288  ),
289  (
290  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
291  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
292  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
293  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
294  ),
295  (
296  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
297  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
298  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
299  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
300  )
301 };
302 
303 static const spi_conf_t spi_config[] = {
304  {
305  .dev = SPI0,
306  .pin_miso = GPIO_PIN(PORT_D, 3),
307  .pin_mosi = GPIO_PIN(PORT_D, 2),
308  .pin_clk = GPIO_PIN(PORT_D, 1),
309  .pin_cs = {
310  GPIO_PIN(PORT_D, 0),
311  GPIO_PIN(PORT_D, 4),
312  GPIO_PIN(PORT_D, 5),
313  GPIO_PIN(PORT_D, 6),
314  GPIO_UNDEF
315  },
316  .pcr = GPIO_AF_2,
317  .simmask = SIM_SCGC6_SPI0_MASK
318  },
319  {
320  .dev = SPI1,
321  .pin_miso = GPIO_PIN(PORT_E, 3),
322  .pin_mosi = GPIO_PIN(PORT_E, 1),
323  .pin_clk = GPIO_PIN(PORT_E, 2),
324  .pin_cs = {
325  GPIO_PIN(PORT_E, 4),
326  GPIO_UNDEF,
327  GPIO_UNDEF,
328  GPIO_UNDEF,
329  GPIO_UNDEF
330  },
331  .pcr = GPIO_AF_2,
332  .simmask = SIM_SCGC6_SPI1_MASK
333  }
334 };
335 
336 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
337 
343 static const i2c_conf_t i2c_config[] = {
344  {
345  .i2c = I2C0,
346  .scl_pin = GPIO_PIN(PORT_B, 2),
347  .sda_pin = GPIO_PIN(PORT_B, 1),
348  .freq = CLOCK_BUSCLOCK,
349  .speed = I2C_SPEED_FAST,
350  .irqn = I2C0_IRQn,
351  .scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
352  .sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
353  },
354 };
355 #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
356 #define I2C_0_ISR (isr_i2c0)
357 #define I2C_1_ISR (isr_i2c1)
358 
360 #ifdef __cplusplus
361 }
362 #endif
363 
364 #endif /* PERIPH_CONF_H */
365 
fast mode: ~400kbit/s
cc2538_uart_t * dev
pointer to the used UART device
I2C configuration options.
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
SPI_Type * dev
SPI device to use.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
FLL Engaged External Mode.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
Clock configuration for Kinetis CPUs.
for 31.25-39.0625 kHz crystal
I2C_Type * i2c
Pointer to hardware module registers.
UART device configuration.
DAC line configuration data.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.