boards/nucleo144-f722/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 216MHz */
37 #define CLOCK_CORECLOCK (216000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (216)
55 #define CLOCK_PLL_P (2)
56 #define CLOCK_PLL_Q (9)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART3,
85  .rcc_mask = RCC_APB1ENR_USART3EN,
86  .rx_pin = GPIO_PIN(PORT_D, 9),
87  .tx_pin = GPIO_PIN(PORT_D, 8),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART3_IRQn,
92 #ifdef UART_USE_DMA
93  .dma_stream = 6,
94  .dma_chan = 4
95 #endif
96  },
97  {
98  .dev = USART6,
99  .rcc_mask = RCC_APB2ENR_USART6EN,
100  .rx_pin = GPIO_PIN(PORT_G, 9),
101  .tx_pin = GPIO_PIN(PORT_G, 14),
102  .rx_af = GPIO_AF8,
103  .tx_af = GPIO_AF8,
104  .bus = APB2,
105  .irqn = USART6_IRQn,
106 #ifdef UART_USE_DMA
107  .dma_stream = 5,
108  .dma_chan = 4
109 #endif
110  },
111  {
112  .dev = USART2,
113  .rcc_mask = RCC_APB1ENR_USART2EN,
114  .rx_pin = GPIO_PIN(PORT_D, 6),
115  .tx_pin = GPIO_PIN(PORT_D, 5),
116  .rx_af = GPIO_AF7,
117  .tx_af = GPIO_AF7,
118  .bus = APB1,
119  .irqn = USART2_IRQn,
120 #ifdef UART_USE_DMA
121  .dma_stream = 4,
122  .dma_chan = 4
123 #endif
124  }
125 };
126 
127 #define UART_0_ISR (isr_usart3)
128 #define UART_0_DMA_ISR (isr_dma1_stream6)
129 #define UART_1_ISR (isr_usart6)
130 #define UART_1_DMA_ISR (isr_dma1_stream5)
131 #define UART_2_ISR (isr_usart2)
132 #define UART_2_DMA_ISR (isr_dma1_stream4)
133 
134 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
135 
141 #define ADC_NUMOF (0)
142 
144 #ifdef __cplusplus
145 }
146 #endif
147 
148 #endif /* PERIPH_CONF_H */
149 
use alternate function 7
void * dev
UART, USART or LEUART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
UART device configuration.
Timer configuration.