boards/nz32-sc151/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Fundacion Inria Chile
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSI (16000000U) /* internal oscillator */
33 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
34 
35 /* configuration of PLL prescaler and multiply values */
36 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
37 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
38 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
39 /* configuration of peripheral bus clock prescalers */
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
43 /* configuration of flash access cycles */
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM5,
59  .max = 0xffffffff,
60  .rcc_mask = RCC_APB1ENR_TIM5EN,
61  .bus = APB1,
62  .irqn = TIM5_IRQn
63  }
64 };
65 
66 #define TIMER_0_ISR (isr_tim5)
67 
68 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
69 
75 static const uart_conf_t uart_config[] = {
76  {
77  .dev = USART3,
78  .rcc_mask = RCC_APB1ENR_USART3EN,
79  .rx_pin = GPIO_PIN(PORT_B, 11),
80  .tx_pin = GPIO_PIN(PORT_B, 10),
81  .rx_af = GPIO_AF7,
82  .tx_af = GPIO_AF7,
83  .bus = APB1,
84  .irqn = USART3_IRQn
85  },
86  {
87  .dev = USART2,
88  .rcc_mask = RCC_APB1ENR_USART2EN,
89  .rx_pin = GPIO_PIN(PORT_A, 3),
90  .tx_pin = GPIO_PIN(PORT_A, 2),
91  .rx_af = GPIO_AF7,
92  .tx_af = GPIO_AF7,
93  .bus = APB1,
94  .irqn = USART2_IRQn
95  },
96  {
97  .dev = USART1,
98  .rcc_mask = RCC_APB2ENR_USART1EN,
99  .rx_pin = GPIO_PIN(PORT_A, 10),
100  .tx_pin = GPIO_PIN(PORT_A, 9),
101  .rx_af = GPIO_AF7,
102  .tx_af = GPIO_AF7,
103  .bus = APB2,
104  .irqn = USART1_IRQn
105  }
106 };
107 
108 #define UART_0_ISR (isr_usart3)
109 #define UART_1_ISR (isr_usart2)
110 #define UART_2_ISR (isr_usart1)
111 
112 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
113 
119 static const pwm_conf_t pwm_config[] = {
120  {
121  .dev = TIM3,
122  .rcc_mask = RCC_APB1ENR_TIM3EN,
123  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
124  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
125  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
126  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
127  .af = GPIO_AF2,
128  .bus = APB1
129  }
130 };
131 
132 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
133 
142 static const uint8_t spi_divtable[2][5] = {
143  { /* for APB1 @ 32000000Hz */
144  7, /* -> 125000Hz */
145  5, /* -> 500000Hz */
146  4, /* -> 1000000Hz */
147  2, /* -> 4000000Hz */
148  1 /* -> 8000000Hz */
149  },
150  { /* for APB2 @ 32000000Hz */
151  7, /* -> 125000Hz */
152  5, /* -> 500000Hz */
153  4, /* -> 1000000Hz */
154  2, /* -> 4000000Hz */
155  1 /* -> 8000000Hz */
156  }
157 };
158 
159 static const spi_conf_t spi_config[] = {
160  {
161  .dev = SPI1,
162  .mosi_pin = GPIO_PIN(PORT_B, 5),
163  .miso_pin = GPIO_PIN(PORT_B, 4),
164  .sclk_pin = GPIO_PIN(PORT_B, 3),
165  .cs_pin = GPIO_UNDEF,
166  .af = GPIO_AF5,
167  .rccmask = RCC_APB2ENR_SPI1EN,
168  .apbbus = APB2
169  },
170  {
171  .dev = SPI2,
172  .mosi_pin = GPIO_PIN(PORT_B, 15),
173  .miso_pin = GPIO_PIN(PORT_B, 14),
174  .sclk_pin = GPIO_PIN(PORT_B, 13),
175  .cs_pin = GPIO_UNDEF,
176  .af = GPIO_AF5,
177  .rccmask = RCC_APB1ENR_SPI2EN,
178  .apbbus = APB1
179  },
180  {
181  .dev = SPI3,
182  .mosi_pin = GPIO_PIN(PORT_C, 12),
183  .miso_pin = GPIO_PIN(PORT_C, 11),
184  .sclk_pin = GPIO_PIN(PORT_C, 10),
185  .cs_pin = GPIO_UNDEF,
186  .af = GPIO_AF6,
187  .rccmask = RCC_APB1ENR_SPI3EN,
188  .apbbus = APB1
189  }
190 };
191 
192 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
193 
199 #define I2C_NUMOF (1)
200 #define I2C_0_EN 1
201 #define I2C_IRQ_PRIO 1
202 #define I2C_APBCLK (36000000U) /* Configurable from 2MHz to 50Mhz, steps of 2Mhz */
203 
204 /* I2C 0 device configuration */
205 #define I2C_0_EVT_ISR isr_i2c1_ev
206 #define I2C_0_ERR_ISR isr_i2c1_er
207 
208 static const i2c_conf_t i2c_config[] = {
209  /* device, port, scl-, sda-pin-number, I2C-AF, ER-IRQn, EV-IRQn */
210  {I2C1, GPIO_PIN(PORT_B, 8), GPIO_PIN(PORT_B, 9),
211  GPIO_OD_PU, GPIO_AF4, I2C1_ER_IRQn, I2C1_EV_IRQn}
212 };
219 #define RTC_NUMOF (1U)
220 
226 #define ADC_CONFIG { \
227  { GPIO_PIN(PORT_C, 0), 10 }, \
228  { GPIO_PIN(PORT_C, 1), 11 }, \
229  { GPIO_PIN(PORT_C, 2), 12 }, \
230  /* ADC Temperature channel */ \
231  { GPIO_UNDEF, 16 }, \
232  /* ADC VREF channel */ \
233  { GPIO_UNDEF, 17 }, \
234 }
235 
236 #define ADC_NUMOF (5)
237 
243 static const dac_conf_t dac_config[] = {
244  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
245  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
246 };
247 
248 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
249 
252 #ifdef __cplusplus
253 }
254 #endif
255 
256 #endif /* PERIPH_CONF_H */
257 
use alternate function 4
use alternate function 7
void * dev
UART, USART or LEUART device used.
I2C configuration options.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
gpio_t pin
pin connected to the line
use alternate function 6
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
DAC line configuration data.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.