boards/pba-d-01-kw2x/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 static const clock_config_t clock_config = {
37  /*
38  * This configuration results in the system running from the PLL output with
39  * the following clock frequencies:
40  * Core: 48 MHz
41  * Bus: 48 MHz
42  * Flash: 24 MHz
43  */
44  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
45  SIM_CLKDIV1_OUTDIV4(1),
46  .rtc_clc = 0, /* External load caps on the FRDM-K22F board */
47  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
48  .clock_flags =
49  /* No OSC0_EN, use modem clock from EXTAL0 */
52  0,
53  .default_mode = KINETIS_MCG_MODE_PEE,
54  /* The modem generates a 4 MHz clock signal */
55  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
56  .osc_clc = 0, /* OSC0 is unused*/
57  .oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL0 for external clock */
58  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
59  .fll_frdiv = MCG_C1_FRDIV(0b010), /* Divide by 128 */
60  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
61  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FLL freq = 40 MHz */
62  .pll_prdiv = MCG_C5_PRDIV0(0b00001), /* Divide by 2 */
63  .pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 48 MHz */
64 };
65 #define CLOCK_CORECLOCK (48000000ul)
66 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
67 
73 #define PIT_NUMOF (2U)
74 #define PIT_CONFIG { \
75  { \
76  .prescaler_ch = 0, \
77  .count_ch = 1, \
78  }, \
79  { \
80  .prescaler_ch = 2, \
81  .count_ch = 3, \
82  }, \
83  }
84 #define LPTMR_NUMOF (0U)
85 #define LPTMR_CONFIG {}
86 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
87 
88 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
89 #define PIT_ISR_0 isr_pit1
90 #define PIT_ISR_1 isr_pit3
91 #define LPTMR_ISR_0 isr_lptmr0
92 
98 static const uart_conf_t uart_config[] = {
99  {
100  .dev = UART2,
101  .freq = CLOCK_BUSCLOCK,
102  .pin_rx = GPIO_PIN(PORT_D, 2),
103  .pin_tx = GPIO_PIN(PORT_D, 3),
104  .pcr_rx = PORT_PCR_MUX(3),
105  .pcr_tx = PORT_PCR_MUX(3),
106  .irqn = UART2_RX_TX_IRQn,
107  .scgc_addr = &SIM->SCGC4,
108  .scgc_bit = SIM_SCGC4_UART2_SHIFT,
109  .mode = UART_MODE_8N1,
110  .type = KINETIS_UART,
111  },
112  {
113  .dev = UART0,
114  .freq = CLOCK_CORECLOCK,
115  .pin_rx = GPIO_PIN(PORT_D, 6),
116  .pin_tx = GPIO_PIN(PORT_D, 7),
117  .pcr_rx = PORT_PCR_MUX(3),
118  .pcr_tx = PORT_PCR_MUX(3),
119  .irqn = UART0_RX_TX_IRQn,
120  .scgc_addr = &SIM->SCGC4,
121  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
122  .mode = UART_MODE_8N1,
123  .type = KINETIS_UART,
124  }
125 };
126 
127 #define UART_0_ISR (isr_uart2_rx_tx)
128 #define UART_1_ISR (isr_uart0_rx_tx)
129 
130 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
131 
137 static const adc_conf_t adc_config[] = {
138  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 2), .chan = 1 },
139  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 3), .chan = 1 },
140  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 7), .chan = 22 },
141  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 5), .chan = 6 },
142  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 0), .chan = 10 },
143  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 1), .chan = 11 }
144 };
145 
146 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
147 /*
148  * KW2xD ADC reference settings:
149  * 0: VREFH/VREFL external pin pair
150  * 1-3: reserved
151  */
152 #define ADC_REF_SETTING 0
153 
159 static const pwm_conf_t pwm_config[] = {
160  {
161  .ftm = FTM0,
162  .chan = {
163  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
164  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
165  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
166  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
167  },
168  .chan_numof = 4,
169  .ftm_num = 0
170  }
171 };
172 
173 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
174 
187 static const uint32_t spi_clk_config[] = {
188  (
189  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
190  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
191  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
192  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
193  ),
194  (
195  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
196  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
197  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
198  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
199  ),
200  (
201  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
202  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
203  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
204  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
205  ),
206  (
207  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
208  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
209  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
210  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
211  ),
212  (
213  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
214  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
215  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
216  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
217  )
218 };
219 
220 static const spi_conf_t spi_config[] = {
221  {
222  .dev = SPI0,
223  .pin_miso = GPIO_PIN(PORT_C, 7),
224  .pin_mosi = GPIO_PIN(PORT_C, 6),
225  .pin_clk = GPIO_PIN(PORT_C, 5),
226  .pin_cs = {
227  GPIO_PIN(PORT_C, 4),
228  GPIO_UNDEF,
229  GPIO_UNDEF,
230  GPIO_UNDEF,
231  GPIO_UNDEF
232  },
233  .pcr = GPIO_AF_2,
234  .simmask = SIM_SCGC6_SPI0_MASK
235  },
236  {
237  .dev = SPI1,
238  .pin_miso = GPIO_PIN(PORT_B, 17),
239  .pin_mosi = GPIO_PIN(PORT_B, 16),
240  .pin_clk = GPIO_PIN(PORT_B, 11),
241  .pin_cs = {
242  GPIO_PIN(PORT_B, 10),
243  GPIO_UNDEF,
244  GPIO_UNDEF,
245  GPIO_UNDEF,
246  GPIO_UNDEF
247  },
248  .pcr = GPIO_AF_2,
249  .simmask = SIM_SCGC6_SPI1_MASK
250  }
251 };
252 
253 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
254 
261 #define I2C_NUMOF (1U)
262 #define I2C_0_EN 1
263 /* Low (10 kHz): MUL = 2, SCL divider = 2560, total: 5120 */
264 #define KINETIS_I2C_F_ICR_LOW (0x3D)
265 #define KINETIS_I2C_F_MULT_LOW (1)
266 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
267 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
268 #define KINETIS_I2C_F_MULT_NORMAL (1)
269 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
270 #define KINETIS_I2C_F_ICR_FAST (0x17)
271 #define KINETIS_I2C_F_MULT_FAST (0)
272 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
273 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
274 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
275 
276 /* I2C 0 device configuration */
277 #define I2C_0_DEV I2C1
278 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
279 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
280 #define I2C_0_IRQ I2C1_IRQn
281 #define I2C_0_IRQ_HANDLER isr_i2c1
282 /* I2C 0 pin configuration */
283 #define I2C_0_PORT PORTE
284 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
285 #define I2C_0_PIN_AF 6
286 #define I2C_0_SDA_PIN 0
287 #define I2C_0_SCL_PIN 1
288 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
289 
296 #define RTT_NUMOF (1U)
297 #define RTC_NUMOF (1U)
298 #define RTT_DEV RTC
299 #define RTT_IRQ RTC_IRQn
300 #define RTT_IRQ_PRIO 10
301 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
302 #define RTT_ISR isr_rtc
303 #define RTT_FREQUENCY (1)
304 #define RTT_MAX_VALUE (0xffffffff)
305 
307 #ifdef __cplusplus
308 }
309 #endif
310 
311 #endif /* PERIPH_CONF_H */
312 
cc2538_uart_t * dev
pointer to the used UART device
PLL Engaged External Mode.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
Clock configuration for Kinetis CPUs.
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.