boards/pba-d-01-kw2x/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 static const clock_config_t clock_config = {
37  /*
38  * This configuration results in the system running from the PLL output with
39  * the following clock frequencies:
40  * Core: 48 MHz
41  * Bus: 48 MHz
42  * Flash: 24 MHz
43  */
44  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
45  SIM_CLKDIV1_OUTDIV4(1),
46  .default_mode = KINETIS_MCG_MODE_PEE,
47  /* The modem generates a 4 MHz clock signal */
48  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
49  .fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
50  .oscsel = 0, /* Use EXTAL0 for external clock */
51  .clc = 0, /* OSC0 is unused*/
52  .fll_frdiv = 0b010, /* Divide by 128 */
53  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
54  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FLL freq = 40 MHz */
55  .pll_prdiv = 0b00001, /* Divide by 2 */
56  .pll_vdiv = 0b00000, /* Multiply by 24 => PLL freq = 48 MHz */
57  .enable_oscillator = false, /* Use modem clock from EXTAL0 */
58  .select_fast_irc = true,
59  .enable_mcgirclk = false,
60 };
61 #define CLOCK_CORECLOCK (48000000ul)
62 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
63 
69 #define PIT_NUMOF (2U)
70 #define PIT_CONFIG { \
71  { \
72  .prescaler_ch = 0, \
73  .count_ch = 1, \
74  }, \
75  { \
76  .prescaler_ch = 2, \
77  .count_ch = 3, \
78  }, \
79  }
80 #define LPTMR_NUMOF (0U)
81 #define LPTMR_CONFIG {}
82 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
83 
84 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
85 #define PIT_ISR_0 isr_pit1
86 #define PIT_ISR_1 isr_pit3
87 #define LPTMR_ISR_0 isr_lptmr0
88 
95 static const uart_conf_t uart_config[] = {
96  {
97  .dev = UART2,
98  .freq = CLOCK_BUSCLOCK,
99  .pin_rx = GPIO_PIN(PORT_D, 2),
100  .pin_tx = GPIO_PIN(PORT_D, 3),
101  .pcr_rx = PORT_PCR_MUX(3),
102  .pcr_tx = PORT_PCR_MUX(3),
103  .irqn = UART2_RX_TX_IRQn,
104  .scgc_addr = &SIM->SCGC4,
105  .scgc_bit = SIM_SCGC4_UART2_SHIFT,
106  .mode = UART_MODE_8N1,
107  .type = KINETIS_UART,
108  },
109  {
110  .dev = UART0,
111  .freq = CLOCK_CORECLOCK,
112  .pin_rx = GPIO_PIN(PORT_D, 6),
113  .pin_tx = GPIO_PIN(PORT_D, 7),
114  .pcr_rx = PORT_PCR_MUX(3),
115  .pcr_tx = PORT_PCR_MUX(3),
116  .irqn = UART0_RX_TX_IRQn,
117  .scgc_addr = &SIM->SCGC4,
118  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
119  .mode = UART_MODE_8N1,
120  .type = KINETIS_UART,
121  }
122 };
123 
124 #define UART_0_ISR (isr_uart2_rx_tx)
125 #define UART_1_ISR (isr_uart0_rx_tx)
126 
127 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
128 
134 static const adc_conf_t adc_config[] = {
135  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 2), .chan = 1 },
136  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 3), .chan = 1 },
137  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 7), .chan = 22 },
138  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 5), .chan = 6 },
139  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 0), .chan = 10 },
140  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 1), .chan = 11 }
141 };
142 
143 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
144 
150 static const pwm_conf_t pwm_config[] = {
151  {
152  .ftm = FTM0,
153  .chan = {
154  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
155  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
156  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
157  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
158  },
159  .chan_numof = 4,
160  .ftm_num = 0
161  }
162 };
163 
164 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
165 
178 static const uint32_t spi_clk_config[] = {
179  (
180  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
181  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
182  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
183  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
184  ),
185  (
186  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
187  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
188  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
189  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
190  ),
191  (
192  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
193  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
194  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
195  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
196  ),
197  (
198  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
199  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
200  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
201  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
202  ),
203  (
204  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
205  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
206  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
207  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
208  )
209 };
210 
211 static const spi_conf_t spi_config[] = {
212  {
213  .dev = SPI0,
214  .pin_miso = GPIO_PIN(PORT_C, 7),
215  .pin_mosi = GPIO_PIN(PORT_C, 6),
216  .pin_clk = GPIO_PIN(PORT_C, 5),
217  .pin_cs = {
218  GPIO_PIN(PORT_C, 4),
219  GPIO_UNDEF,
220  GPIO_UNDEF,
221  GPIO_UNDEF,
222  GPIO_UNDEF
223  },
224  .pcr = GPIO_AF_2,
225  .simmask = SIM_SCGC6_SPI0_MASK
226  },
227  {
228  .dev = SPI1,
229  .pin_miso = GPIO_PIN(PORT_B, 17),
230  .pin_mosi = GPIO_PIN(PORT_B, 16),
231  .pin_clk = GPIO_PIN(PORT_B, 11),
232  .pin_cs = {
233  GPIO_PIN(PORT_B, 10),
234  GPIO_UNDEF,
235  GPIO_UNDEF,
236  GPIO_UNDEF,
237  GPIO_UNDEF
238  },
239  .pcr = GPIO_AF_2,
240  .simmask = SIM_SCGC6_SPI1_MASK
241  }
242 };
243 
244 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
245 
252 #define I2C_NUMOF (1U)
253 #define I2C_0_EN 1
254 /* Low (10 kHz): MUL = 2, SCL divider = 2560, total: 5120 */
255 #define KINETIS_I2C_F_ICR_LOW (0x3D)
256 #define KINETIS_I2C_F_MULT_LOW (1)
257 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
258 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
259 #define KINETIS_I2C_F_MULT_NORMAL (1)
260 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
261 #define KINETIS_I2C_F_ICR_FAST (0x17)
262 #define KINETIS_I2C_F_MULT_FAST (0)
263 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
264 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
265 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
266 
267 /* I2C 0 device configuration */
268 #define I2C_0_DEV I2C1
269 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
270 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
271 #define I2C_0_IRQ I2C1_IRQn
272 #define I2C_0_IRQ_HANDLER isr_i2c1
273 /* I2C 0 pin configuration */
274 #define I2C_0_PORT PORTE
275 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
276 #define I2C_0_PIN_AF 6
277 #define I2C_0_SDA_PIN 0
278 #define I2C_0_SCL_PIN 1
279 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
280 
287 #define RTT_NUMOF (1U)
288 #define RTC_NUMOF (1U)
289 #define RTT_DEV RTC
290 #define RTT_IRQ RTC_IRQn
291 #define RTT_IRQ_PRIO 10
292 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
293 #define RTT_ISR isr_rtc
294 #define RTT_FREQUENCY (1)
295 #define RTT_MAX_VALUE (0xffffffff)
296 
298 #ifdef __cplusplus
299 }
300 #endif
301 
302 #endif /* PERIPH_CONF_H */
303 
void * dev
UART, USART or LEUART device used.
FTM_Type * ftm
used FTM
PLL Engaged External Mode.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
Clock configuration for Kinetis CPUs.
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.