cc2538/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * 2017 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdio.h>
26 
27 #include "vendor/hw_soc_adc.h"
28 
29 #include "cpu.h"
30 #include "vendor/hw_ssi.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
39 #define CPUID_ADDR (&IEEE_ADDR_MSWORD)
40 
44 #define CPUID_LEN (8U)
45 
50 #define HAVE_GPIO_T
51 typedef uint32_t gpio_t;
58 #define PROVIDES_PM_SET_LOWEST_CORTEXM
59 
64 #define GPIO_UNDEF (0xffffffff)
65 
69 #define GPIO_MUX_NONE (0xff)
70 
76 #define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
77  (port << GPIO_PORTNUM_SHIFT)) | pin)
78 
86 void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
87 
96 void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func);
97 
102 #define PERIPH_I2C_NEED_READ_REG
103 #define PERIPH_I2C_NEED_READ_REGS
104 #define PERIPH_I2C_NEED_WRITE_REG
105 #define PERIPH_I2C_NEED_WRITE_REGS
106 
112 #define HAVE_I2C_SPEED_T
113 typedef enum {
114  I2C_SPEED_LOW = 0x01,
115  I2C_SPEED_NORMAL = 100000U,
116  I2C_SPEED_FAST = 400000U,
118  I2C_SPEED_HIGH = 0x03,
119 } i2c_speed_t;
124 typedef struct {
126  gpio_t scl_pin;
127  gpio_t sda_pin;
128 } i2c_conf_t;
129 
134 #define PERIPH_SPI_NEEDS_INIT_CS
135 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
136 #define PERIPH_SPI_NEEDS_TRANSFER_REG
137 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
138 
144 #define HAVE_GPIO_MODE_T
145 typedef enum {
146  GPIO_IN = ((uint8_t)OVERRIDE_DISABLE),
147  GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG),
148  GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN),
149  GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP),
150  GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE),
151  GPIO_OD = (0xff),
152  GPIO_OD_PU = (0xff)
153 } gpio_mode_t;
161 typedef struct {
163  gpio_t rx_pin;
164  gpio_t tx_pin;
165  gpio_t cts_pin;
166  gpio_t rts_pin;
167 } uart_conf_t;
174 #define HAVE_SPI_MODE_T
175 typedef enum {
177  SPI_MODE_1 = (SSI_CR0_SPH),
178  SPI_MODE_2 = (SSI_CR0_SPO),
179  SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
180 } spi_mode_t;
187 #define HAVE_SPI_CLK_T
188 typedef enum {
194 } spi_clk_t;
200 typedef struct {
201  uint8_t cpsr;
202  uint8_t scr;
204 
205 #ifndef BOARD_HAS_SPI_CLK_CONF
206 
213 static const spi_clk_conf_t spi_clk_config[] = {
214  { .cpsr = 64, .scr = 4 }, /* 100khz */
215  { .cpsr = 16, .scr = 4 }, /* 400khz */
216  { .cpsr = 32, .scr = 0 }, /* 1.0MHz */
217  { .cpsr = 2, .scr = 2 }, /* 5.3MHz */
218  { .cpsr = 2, .scr = 1 } /* 8.0MHz */
219 };
220 #endif /* BOARD_HAS_SPI_CLK_CONF */
221 
226 typedef struct {
227  uint8_t num;
228  gpio_t mosi_pin;
229  gpio_t miso_pin;
230  gpio_t sck_pin;
231  gpio_t cs_pin;
232 } spi_conf_t;
241 typedef struct {
242  uint_fast8_t chn;
243  uint_fast8_t cfg;
244 } timer_conf_t;
245 
250 #define HAVE_ADC_RES_T
251 typedef enum {
252  ADC_RES_6BIT = (0xa00),
253  ADC_RES_7BIT = (0 << 4),
254  ADC_RES_8BIT = (0xb00),
255  ADC_RES_9BIT = (1 << 4),
256  ADC_RES_10BIT = (2 << 4),
257  ADC_RES_12BIT = (3 << 4),
258  ADC_RES_14BIT = (0xc00),
259  ADC_RES_16BIT = (0xd00),
260 } adc_res_t;
266 typedef gpio_t adc_conf_t;
267 
272 #define SOC_ADC_ADCCON3_EREF_INT (0 << SOC_ADC_ADCCON3_EREF_S)
273 #define SOC_ADC_ADCCON3_EREF_EXT (1 << SOC_ADC_ADCCON3_EREF_S)
274 #define SOC_ADC_ADCCON3_EREF_AVDD5 (2 << SOC_ADC_ADCCON3_EREF_S)
275 #define SOC_ADC_ADCCON3_EREF_DIFF (3 << SOC_ADC_ADCCON3_EREF_S)
282 #define SOCADC_7_BIT_RSHIFT (9U)
283 #define SOCADC_9_BIT_RSHIFT (7U)
284 #define SOCADC_10_BIT_RSHIFT (6U)
285 #define SOCADC_12_BIT_RSHIFT (4U)
288 #ifdef __cplusplus
289 }
290 #endif
291 
292 #endif /* PERIPH_CPU_H */
293 
fast mode: ~400kbit/s
CPOL=0, CPHA=1.
ADC resolution: 7 bit.
cc2538_uart_t * dev
pointer to the used UART device
I2C configuration options.
gpio_t cs_pin
pin used for CS
ADC resolution: 12 bit.
ADC resolution: 9 bit.
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
uint8_t num
number of SSI device, i.e.
gpio_t miso_pin
pin used for MISO
gpio_t scl_pin
pin used for SCL
CPOL=0, CPHA=0.
drive the SPI bus with 100KHz
drive the SPI bus with 400KHz
gpio_t rx_pin
pin used for RX
uint_fast8_t cfg
timer config word
gpio_t rts_pin
RTS pin - set to GPIO_UNDEF when not using.
not supported by hardware
ADC resolution: 10 bit.
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
not supported by hardware
Datafields for static SPI clock configuration values.
gpio_t sck_pin
pin used for SCK
drive the SPI bus with 5MHz
not supported by hardware
uint_fast8_t chn
number of channels
gpio_t tx_pin
pin used for TX
not supported by hardware
drive the SPI bus with 10MHz
i2c_speed_t speed
baudrate used for the bus
drive the SPI bus with 1MHz
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
Configure an alternate function for the given pin.
void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func)
Configure an alternate function for the given pin.
UART device configuration.
input, no pull
uint8_t scr
SCR clock divider.
gpio_t cts_pin
CTS pin - set to GPIO_UNDEF when not using.
UART component registers.
Definition: cc2538_uart.h:32
not supported
gpio_t sda_pin
pin used for SDA
CPOL=1, CPHA=0.
SPI module configuration options.
normal mode: ~100kbit/s
input, pull-down
uint8_t cpsr
CPSR clock divider.
Timer configuration.
gpio_t mosi_pin
pin used for MOSI