efm32_common/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CPU_H
21 #define PERIPH_CPU_H
22 
23 #include "mutex.h"
24 
25 #include "cpu_conf.h"
26 
27 #include "em_adc.h"
28 #include "em_cmu.h"
29 #include "em_device.h"
30 #include "em_gpio.h"
31 #include "em_usart.h"
32 #ifdef _SILICON_LABS_32B_SERIES_0
33 #include "em_dac.h"
34 #endif
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
44 #ifndef LOW_POWER_ENABLED
45 #define LOW_POWER_ENABLED (1)
46 #endif
47 
53 #define ADC_MODE(x, y) ((y << 4) | x)
54 
58 #define ADC_MODE_UNDEF (0xff)
59 
60 #ifndef DOXYGEN
61 
65 #define HAVE_ADC_RES_T
66 typedef enum {
67  ADC_RES_6BIT = ADC_MODE(adcRes6Bit, 0),
68  ADC_RES_8BIT = ADC_MODE(adcRes8Bit, 0),
69  ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),
70  ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),
73 } adc_res_t;
75 #endif /* ndef DOXYGEN */
76 
80 typedef struct {
81  ADC_TypeDef *dev;
82  CMU_Clock_TypeDef cmu;
83 } adc_conf_t;
84 
88 typedef struct {
89  uint8_t dev;
90 #ifdef _SILICON_LABS_32B_SERIES_0
91  ADC_SingleInput_TypeDef input;
92 #else
93  ADC_PosSel_TypeDef input;
94 #endif
95  ADC_Ref_TypeDef reference;
96  ADC_AcqTime_TypeDef acq_time;
98 
102 #define CPUID_LEN (8U)
103 
104 #if defined(DAC_COUNT) && DAC_COUNT > 0
105 
108 typedef struct {
109  DAC_TypeDef *dev;
110  CMU_Clock_TypeDef cmu;
111 } dac_conf_t;
112 
116 typedef struct {
117  uint8_t dev;
118  uint8_t index;
119  DAC_Ref_TypeDef ref;
120 } dac_chan_conf_t;
121 #endif
122 
127 #define HAVE_GPIO_T
128 typedef uint32_t gpio_t;
134 #define GPIO_UNDEF (0xffffffff)
135 
139 #define GPIO_PIN(x, y) ((gpio_t) ((x << 4) | y))
140 
144 #define GPIO_MODE(x, y) ((x << 1) | y)
145 
149 enum {
150 #if (_GPIO_PORT_A_PIN_COUNT > 0)
151  PA = gpioPortA,
152 #endif
153 #if (_GPIO_PORT_B_PIN_COUNT > 0)
154  PB = gpioPortB,
155 #endif
156 #if (_GPIO_PORT_C_PIN_COUNT > 0)
157  PC = gpioPortC,
158 #endif
159 #if (_GPIO_PORT_D_PIN_COUNT > 0)
160  PD = gpioPortD,
161 #endif
162 #if (_GPIO_PORT_E_PIN_COUNT > 0)
163  PE = gpioPortE,
164 #endif
165 #if (_GPIO_PORT_F_PIN_COUNT > 0)
166  PF = gpioPortF,
167 #endif
168 #if (_GPIO_PORT_G_PIN_COUNT > 0)
169  PG = gpioPortG,
170 #endif
171 #if (_GPIO_PORT_H_PIN_COUNT > 0)
172  PH = gpioPortH,
173 #endif
174 #if (_GPIO_PORT_I_PIN_COUNT > 0)
175  PI = gpioPortI,
176 #endif
177 #if (_GPIO_PORT_J_PIN_COUNT > 0)
178  PJ = gpioPortJ,
179 #endif
180 #if (_GPIO_PORT_K_PIN_COUNT > 0)
181  PK = gpioPortK
182 #endif
183 };
184 
185 #ifndef DOXYGEN
186 
190 #define HAVE_GPIO_MODE_T
191 typedef enum {
192  GPIO_IN = GPIO_MODE(gpioModeInput, 0),
193  GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),
194  GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),
195  GPIO_OUT = GPIO_MODE(gpioModePushPull, 0),
196  GPIO_OD = GPIO_MODE(gpioModeWiredAnd, 1),
197  GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),
198 } gpio_mode_t;
205 #define HAVE_GPIO_FLANK_T
206 typedef enum {
207  GPIO_FALLING = 2,
208  GPIO_RISING = 1,
209  GPIO_BOTH = 3
210 } gpio_flank_t;
212 #endif /* ndef DOXYGEN */
213 
218 #define HAVE_HWCRYPTO_AES128
219 #ifdef AES_CTRL_AES256
220 #define HAVE_HWCRYPTO_AES256
221 #endif
222 #ifdef _SILICON_LABS_32B_SERIES_1
223 #define HAVE_HWCRYPTO_SHA1
224 #define HAVE_HWCRYPTO_SHA256
225 #endif
226 
228 #ifndef DOXYGEN
229 
233 #define HAVE_I2C_SPEED_T
234 typedef enum {
235  I2C_SPEED_LOW = 10000,
236  I2C_SPEED_NORMAL = 100000,
237  I2C_SPEED_FAST = 400000,
238  I2C_SPEED_FAST_PLUS = 1000000,
239  I2C_SPEED_HIGH = 3400000,
240 } i2c_speed_t;
242 #endif /* ndef DOXYGEN */
243 
247 typedef struct {
248  I2C_TypeDef *dev;
249  gpio_t sda_pin;
250  gpio_t scl_pin;
251  uint32_t loc;
252  CMU_Clock_TypeDef cmu;
254 } i2c_conf_t;
255 
259 typedef struct {
260  uint8_t index;
261  gpio_t pin;
262  uint32_t loc;
264 
268 typedef struct {
269  TIMER_TypeDef *dev;
270  CMU_Clock_TypeDef cmu;
272  uint8_t channels;
274 } pwm_conf_t;
275 
276 #ifndef DOXYGEN
277 
281 #define HAVE_SPI_MODE_T
282 typedef enum {
283  SPI_MODE_0 = usartClockMode0,
284  SPI_MODE_1 = usartClockMode1,
285  SPI_MODE_2 = usartClockMode2,
286  SPI_MODE_3 = usartClockMode3
287 } spi_mode_t;
294 #define HAVE_SPI_CLK_T
295 typedef enum {
296  SPI_CLK_100KHZ = 100000,
297  SPI_CLK_400KHZ = 400000,
298  SPI_CLK_1MHZ = 1000000,
299  SPI_CLK_5MHZ = 5000000,
300  SPI_CLK_10MHZ = 10000000
301 } spi_clk_t;
303 #endif /* ndef DOXYGEN */
304 
308 typedef struct {
309  USART_TypeDef *dev;
310  gpio_t mosi_pin;
311  gpio_t miso_pin;
312  gpio_t clk_pin;
313  uint32_t loc;
314  CMU_Clock_TypeDef cmu;
316 } spi_dev_t;
317 
322 #define PERIPH_SPI_NEEDS_INIT_CS
323 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
324 #define PERIPH_SPI_NEEDS_TRANSFER_REG
325 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
326 
335 typedef struct {
336  TIMER_TypeDef *dev;
337  CMU_Clock_TypeDef cmu;
338 } timer_dev_t;
339 
340 typedef struct {
344 } timer_conf_t;
350 typedef struct {
351  void *dev;
352  gpio_t rx_pin;
353  gpio_t tx_pin;
354  uint32_t loc;
355  CMU_Clock_TypeDef cmu;
357 } uart_conf_t;
358 
362 #define PM_NUM_MODES (3U)
363 
364 #ifdef __cplusplus
365 }
366 #endif
367 
368 #endif /* PERIPH_CPU_H */
369 
SPI device configuration.
void * dev
UART, USART or LEUART device used.
uint8_t index
TIMER channel to use.
I2C configuration options.
IRQn_Type irq
the devices base IRQ channel
TIMER_TypeDef * dev
TIMER device used.
emit interrupt on rising flank
gpio_t mosi_pin
pin used for MOSI
uint32_t loc
location of USART pins
ADC resolution: 12 bit.
PWM channel configuration.
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
CMU_Clock_TypeDef cmu
the device CMU channel
enum IRQn IRQn_Type
Interrupt Number Definition.
gpio_t miso_pin
pin used for MISO
uint8_t channels
the number of available channels
IRQn_Type irq
the devices base IRQ channel
PWM device configuration.
gpio_t rx_pin
pin used for RX
CMU_Clock_TypeDef cmu
the device CMU channel
emit interrupt on both flanks
CMU_Clock_TypeDef cmu
the device CMU channel
const pwm_chan_conf_t * channel
pointer to first channel config
timer_dev_t timer
the higher numbered timer
uint32_t loc
location of USART pins
ADC_PosSel_TypeDef input
input channel
not supported by hardware
ADC resolution: 10 bit.
CMU_Clock_TypeDef cmu
the device CMU channel
IRQn_Type irq
the devices base IRQ channel
ADC_TypeDef * dev
ADC device used.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
not supported by hardware
gpio_t pin
pin used for pwm
IRQn_Type irq
number of the higher timer IRQ channel
uint32_t loc
location of the pin
not supported by hardware
gpio_t tx_pin
pin used for TX
ADC_Ref_TypeDef reference
channel voltage reference
timer_dev_t prescaler
the lower numbered neighboring timer
not supported by hardware
#define ADC_MODE(x, y)
Internal macro for combining ADC resolution (x) with number of shifts (y).
emit interrupt on falling flank
RIOT synchronization API.
UART device configuration.
input, no pull
I2C_TypeDef * dev
USART device used.
DAC line configuration data.
CMU_Clock_TypeDef cmu
the device CMU channel
uint32_t loc
location of I2C pins
Define timer configuration values.
TIMER_TypeDef * dev
Timer device used.
not supported
gpio_t clk_pin
pin used for CLK
input, pull-down
CMU_Clock_TypeDef cmu
the device CMU channel
ADC channel configuration.
USART_TypeDef * dev
USART device used.
Timer configuration.
#define ADC_MODE_UNDEF
Internal define to note that resolution is not supported.
ADC_AcqTime_TypeDef acq_time
channel acquisition time
IRQn_Type irq
the devices base IRQ channel