STM32 Nucleo-F103

Support for the STM32 Nucleo-F103. More...

Detailed Description

Support for the STM32 Nucleo-F103.

Files

file  boards/nucleo-f103/include/periph_conf.h
 Peripheral MCU configuration for the nucleo-f103 board.
 

Clock settings

Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c
#define CLOCK_CORECLOCK   (72000000U)
 
#define CLOCK_HSE   (8000000U)
 
#define CLOCK_LSE   (1)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 2)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_PLL_PREDIV   (1)
 
#define CLOCK_PLL_MUL   (9)
 

ADC configuration

#define ADC_NUMOF   (0)
 

Timer configuration

static const timer_conf_t timer_config []
 
#define TIMER_0_ISR   isr_tim2
 
#define TIMER_1_ISR   isr_tim3
 
#define TIMER_NUMOF   (sizeof(timer_config) / sizeof(timer_config[0]))
 

UART configuration

static const uart_conf_t uart_config []
 
#define UART_0_ISR   (isr_usart2)
 
#define UART_1_ISR   (isr_usart1)
 
#define UART_2_ISR   (isr_usart3)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 

Real time counter configuration

#define RTT_NUMOF   (1U)
 
#define RTT_IRQ_PRIO   1
 
#define RTT_DEV   RTC
 
#define RTT_IRQ   RTC_IRQn
 
#define RTT_ISR   isr_rtc
 
#define RTT_MAX_VALUE   (0xffffffff)
 
#define RTT_FREQUENCY   (16384) /* in Hz */
 
#define RTT_PRESCALER   (0x1) /* run with ~16 kHz Hz */
 

I2C configuration

#define I2C_NUMOF   (2U)
 
#define I2C_0_EN   1
 
#define I2C_1_EN   0
 
#define I2C_IRQ_PRIO   1
 
#define I2C_APBCLK   (CLOCK_APB1)
 
#define I2C_0_DEV   I2C1
 
#define I2C_0_CLKEN()   (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
 
#define I2C_0_CLKDIS()   (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
 
#define I2C_0_EVT_IRQ   I2C1_EV_IRQn
 
#define I2C_0_EVT_ISR   isr_i2c1_ev
 
#define I2C_0_ERR_IRQ   I2C1_ER_IRQn
 
#define I2C_0_ERR_ISR   isr_i2c1_er
 
#define I2C_0_SCL_PIN   GPIO_PIN(PORT_B, 8) /* remapped */
 
#define I2C_0_SDA_PIN   GPIO_PIN(PORT_B, 9) /* remapped */
 
#define I2C_1_DEV   I2C2
 
#define I2C_1_CLKEN()   (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
 
#define I2C_1_CLKDIS()   (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
 
#define I2C_1_EVT_IRQ   I2C2_EV_IRQn
 
#define I2C_1_EVT_ISR   isr_i2c2_ev
 
#define I2C_1_ERR_IRQ   I2C2_ER_IRQn
 
#define I2C_1_ERR_ISR   isr_i2c2_er
 
#define I2C_1_SCL_PIN   GPIO_PIN(PORT_B, 10)
 
#define I2C_1_SDA_PIN   GPIO_PIN(PORT_B, 11)
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 
#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 

Variable Documentation

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.

Definition at line 205 of file boards/nucleo-f103/include/periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
6,
4,
2,
1
},
{
7,
7,
5,
3,
2
}
}

Definition at line 188 of file boards/nucleo-f103/include/periph_conf.h.

◆ timer_config

const timer_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TIM2,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
},
{
.dev = TIM3,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.bus = APB1,
.irqn = TIM3_IRQn
}
}

Definition at line 70 of file boards/nucleo-f103/include/periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.bus = APB2,
.irqn = USART1_IRQn
},
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_B, 11),
.tx_pin = GPIO_PIN(PORT_B, 10),
.bus = APB1,
.irqn = USART3_IRQn
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 97 of file boards/nucleo-f103/include/periph_conf.h.