STM32 Nucleo-L476

Support for the STM32 Nucleo-L476. More...

Detailed Description

Support for the STM32 Nucleo-L476.

Files

file  boards/nucleo-l476/include/periph_conf.h
 Peripheral MCU configuration for the nucleo-l476 board.
 

Clock system configuration

#define CLOCK_HSE   (0)
 
#define CLOCK_LSE   (0)
 
#define CLOCK_MSI_ENABLE   (1)
 
#define CLOCK_MSI_LSE_PLL   (0)
 
#define CLOCK_CORECLOCK   (80000000U)
 
#define CLOCK_PLL_M   (6)
 
#define CLOCK_PLL_N   (20)
 
#define CLOCK_PLL_R   (2)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV4
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 4)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV2
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 2)
 

Timer configuration

static const timer_conf_t timer_config []
 
#define TIMER_0_ISR   isr_tim5
 
#define TIMER_NUMOF   (sizeof(timer_config) / sizeof(timer_config[0]))
 

UART configuration

static const uart_conf_t uart_config []
 
#define UART_0_ISR   (isr_usart2)
 
#define UART_1_ISR   (isr_usart3)
 
#define UART_2_ISR   (isr_usart1)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 

PWM configuration

static const pwm_conf_t pwm_config []
 
#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 
#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 

ADC configuration

#define ADC_NUMOF   (0)
 

RTT configuration

On the STM32Lx platforms, we always utilize the LPTIM1.

#define RTT_NUMOF   (1)
 
#define RTT_FREQUENCY   (1024U) /* 32768 / 2^n */
 
#define RTT_MAX_VALUE   (0x0000ffff) /* 16-bit timer */
 

RTC configuration

#define RTC_NUMOF   (1)
 

Variable Documentation

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 5
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.

Definition at line 230 of file boards/nucleo-l476/include/periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
5,
3,
1,
0
},
{
7,
6,
4,
2,
1
}
}

Definition at line 213 of file boards/nucleo-l476/include/periph_conf.h.

◆ timer_config

const timer_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TIM5,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM5EN,
.bus = APB1,
.irqn = TIM5_IRQn
}
}

Definition at line 95 of file boards/nucleo-l476/include/periph_conf.h.