STM32 Nucleo32-F031

Support for the STM32 Nucleo32-F031. More...

Detailed Description

Support for the STM32 Nucleo32-F031.

Files

file  boards/nucleo32-f031/include/periph_conf.h
 Peripheral MCU configuration for the nucleo32-f031 board.
 

Clock settings

Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c
#define CLOCK_CORECLOCK   (48000000U)
 
#define CLOCK_HSE   (0U)
 
#define CLOCK_LSE   (0)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE_DIV1 /* max 48MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB2   (CLOCK_APB1)
 
#define CLOCK_PLL_PREDIV   (2)
 
#define CLOCK_PLL_MUL   (12)
 

Timer configuration

static const timer_conf_t timer_config []
 
#define TIMER_0_ISR   isr_tim2
 
#define TIMER_NUMOF   (sizeof(timer_config) / sizeof(timer_config[0]))
 

UART configuration

static const uart_conf_t uart_config []
 
#define UART_0_ISR   (isr_usart1)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 

PWM configuration

static const pwm_conf_t pwm_config []
 
#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 
#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 

RTC configuration

#define RTC_NUMOF   (0U)
 Nucleo-f031 does not have any LSE, current RTC driver does not support LSI as clock source, so disabling RTC.
 

ADC configuration

#define ADC_CONFIG
 
#define ADC_NUMOF   (5)
 

Macro Definition Documentation

◆ ADC_CONFIG

#define ADC_CONFIG
Value:
{ \
{ GPIO_PIN(PORT_A, 0), 0 }, \
{ GPIO_PIN(PORT_A, 1), 1 }, \
{ GPIO_PIN(PORT_A, 3), 3 }, \
{ GPIO_PIN(PORT_A, 4), 4 }, \
{ GPIO_PIN(PORT_A, 7), 7 } \
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 195 of file boards/nucleo32-f031/include/periph_conf.h.

Variable Documentation

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 0
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.

Definition at line 164 of file boards/nucleo32-f031/include/periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
6,
5,
2,
1
},
{
7,
6,
5,
2,
1
}
}

Definition at line 147 of file boards/nucleo32-f031/include/periph_conf.h.

◆ timer_config

const timer_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
}

Definition at line 63 of file boards/nucleo32-f031/include/periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 15),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF1,
.tx_af = GPIO_AF1,
.bus = APB2,
.irqn = USART1_IRQn
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1

Definition at line 82 of file boards/nucleo32-f031/include/periph_conf.h.