kinetis/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2017-2018 Eistec AB
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 #define HAVE_GPIO_T
38 typedef uint16_t gpio_t;
44 #define GPIO_UNDEF (0xffff)
45 
49 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
50 
51 #ifdef SIM_UIDH_UID_MASK
52 /* Kinetis Cortex-M4 has a 128 bit SIM UID */
56 #define CPUID_ADDR (&SIM->UIDH)
57 
61 #define CPUID_LEN (16U)
62 #else /* defined(SIM_UIDH_UID_MASK) */
63 /* Kinetis Cortex-M0+ has a 96 bit SIM UID */
67 #define CPUID_ADDR (&SIM->UIDMH)
68 
71 #define CPUID_LEN (12U)
72 #endif /* defined(SIM_UIDH_UID_MASK) */
73 
83 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
84 
91 #define SPI_HWCS(x) (x)
92 
96 #define SPI_HWCS_NUMOF (5)
97 
102 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
103 #define PERIPH_SPI_NEEDS_TRANSFER_REG 1
104 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
105 
110 #define PERIPH_TIMER_PROVIDES_SET
111 
115 #define PM_NUM_MODES (1U)
116 
117 #ifdef RTC
118 /* All Kinetis CPUs have exactly one RTC hardware module, except for the KL02
119  * family which don't have an RTC at all */
124 #define RTT_NUMOF (1U)
125 #define RTC_NUMOF (1U)
126 #define RTT_FREQUENCY (1)
127 #define RTT_MAX_VALUE (0xffffffff)
128 
129 #endif
130 
131 #ifndef DOXYGEN
132 
136 #define HAVE_GPIO_MODE_T
137 typedef enum {
138  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
139  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
140  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
141  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
142  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
143  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
144 } gpio_mode_t;
146 #endif /* ndef DOXYGEN */
147 
153 typedef enum {
154  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
155  GPIO_AF_GPIO = PORT_PCR_MUX(1),
156  GPIO_AF_2 = PORT_PCR_MUX(2),
157  GPIO_AF_3 = PORT_PCR_MUX(3),
158  GPIO_AF_4 = PORT_PCR_MUX(4),
159  GPIO_AF_5 = PORT_PCR_MUX(5),
160  GPIO_AF_6 = PORT_PCR_MUX(6),
161  GPIO_AF_7 = PORT_PCR_MUX(7),
162 #ifdef PORT_PCR_ODE_MASK
163  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
164 #endif
165  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
166  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
167 } gpio_pcr_t;
168 
169 #ifndef DOXYGEN
170 
174 #define HAVE_GPIO_FLANK_T
175 typedef enum {
176  GPIO_RISING = PORT_PCR_IRQC(0x9),
177  GPIO_FALLING = PORT_PCR_IRQC(0xa),
178  GPIO_BOTH = PORT_PCR_IRQC(0xb),
179 } gpio_flank_t;
181 #endif /* ndef DOXYGEN */
182 
188 enum {
189  PORT_A = 0,
190  PORT_B = 1,
191  PORT_C = 2,
192  PORT_D = 3,
193  PORT_E = 4,
194  PORT_F = 5,
195  PORT_G = 6,
197 };
198 
199 #ifndef DOXYGEN
200 
204 #define HAVE_ADC_RES_T
205 typedef enum {
206  ADC_RES_6BIT = (0xfe),
207  ADC_RES_8BIT = ADC_CFG1_MODE(0),
208  ADC_RES_10BIT = ADC_CFG1_MODE(2),
209  ADC_RES_12BIT = ADC_CFG1_MODE(1),
210  ADC_RES_14BIT = (0xff),
211  ADC_RES_16BIT = ADC_CFG1_MODE(3)
212 } adc_res_t;
215 #if defined(FTM_CnSC_MSB_MASK)
216 
219 #define PWM_CHAN_MAX (4U)
220 
225 #define HAVE_PWM_MODE_T
226 typedef enum {
227  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
228  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
229  PWM_CENTER = (FTM_CnSC_MSB_MASK)
230 } pwm_mode_t;
231 #endif /* defined(FTM_CnSC_MSB_MASK) */
232 #endif /* ndef DOXYGEN */
233 
237 typedef enum {
241 #if defined(UART_C1_M_MASK) || DOXYGEN
242  /* LPUART and UART mode bits coincide, so the same setting for UART works on
243  * the LPUART as well */
244  UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
245 #elif defined(LPUART_CTRL_M_MASK)
246  /* For CPUs which only have the LPUART */
247  UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
248 #endif
250 #if defined(UART_C1_M_MASK) || DOXYGEN
251  UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
252 #elif defined(LPUART_CTRL_M_MASK)
253  /* For CPUs which only have the LPUART */
254  UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
255 #endif
256 } uart_mode_t;
257 
258 #ifndef DOXYGEN
259 
263 #define HAVE_SPI_MODE_T
264 typedef enum {
265  SPI_MODE_0 = 0,
266  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
267  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
268  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
269 } spi_mode_t;
271 #endif /* ndef DOXYGEN */
272 
276 typedef struct {
277  ADC_Type *dev;
278  gpio_t pin;
280  uint8_t chan;
281 } adc_conf_t;
282 
283 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
284 
287 typedef struct {
288  DAC_Type *dev;
289  volatile uint32_t *scgc_addr;
290  uint8_t scgc_bit;
291 } dac_conf_t;
292 #endif
293 
297 typedef struct {
299  uint8_t prescaler_ch;
301  uint8_t count_ch;
302 } pit_conf_t;
303 
307 typedef struct {
309  LPTMR_Type *dev;
311  uint32_t base_freq;
313  uint8_t src;
315  uint8_t irqn;
316 } lptmr_conf_t;
317 
318 #ifdef FTM_CnSC_MSB_MASK
319 
322 typedef struct {
323  FTM_Type* ftm;
324  struct {
325  gpio_t pin;
326  uint8_t af;
327  uint8_t ftm_chan;
328  } chan[PWM_CHAN_MAX];
329  uint8_t chan_numof;
330  uint8_t ftm_num;
331 } pwm_conf_t;
332 #endif
333 
334 #ifndef DOXYGEN
335 #define HAVE_I2C_SPEED_T
336 typedef enum {
337  I2C_SPEED_LOW = 10000ul,
338  I2C_SPEED_NORMAL = 100000ul,
339  I2C_SPEED_FAST = 400000ul,
340  I2C_SPEED_FAST_PLUS = 1000000ul,
341  /* High speed is not supported without external hardware hacks */
342  I2C_SPEED_HIGH = 3400000ul,
343 } i2c_speed_t;
348 #define PERIPH_I2C_NEED_READ_REG
349 #define PERIPH_I2C_NEED_READ_REGS
350 #define PERIPH_I2C_NEED_WRITE_REG
351 #define PERIPH_I2C_NEED_WRITE_REGS
352 
353 #endif /* !defined(DOXYGEN) */
354 
358 typedef struct {
359  I2C_Type *i2c;
360  gpio_t scl_pin;
361  gpio_t sda_pin;
362  uint32_t freq;
363  i2c_speed_t speed;
365  uint32_t scl_pcr;
366  uint32_t sda_pcr;
367 } i2c_conf_t;
368 
372 typedef struct {
373  SPI_Type *dev;
374  gpio_t pin_miso;
375  gpio_t pin_mosi;
376  gpio_t pin_clk;
377  gpio_t pin_cs[SPI_HWCS_NUMOF];
379  uint32_t simmask;
380 } spi_conf_t;
381 
385 enum {
388 };
389 
395 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
396 
397 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
398 
403 typedef enum {
406 } uart_type_t;
407 
411 typedef struct {
412  void *dev;
413  uint32_t freq;
414  gpio_t pin_rx;
415  gpio_t pin_tx;
416  uint32_t pcr_rx;
417  uint32_t pcr_tx;
419  volatile uint32_t *scgc_addr;
420  uint8_t scgc_bit;
422  uart_type_t type;
423 } uart_conf_t;
424 
425 #if !defined(KINETIS_HAVE_PLL)
426 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
427 
430 #define KINETIS_HAVE_PLL 1
431 #else
432 #define KINETIS_HAVE_PLL 0
433 #endif
434 #endif /* !defined(KINETIS_HAVE_PLL) */
435 
439 typedef enum kinetis_mcg_mode {
446 #if KINETIS_HAVE_PLL
449 #endif
452 
456 typedef enum {
458  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
460  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
462  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
464  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
466  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
468  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
470  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
472  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
474 
478 typedef enum {
479  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
480  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
481  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
483 
490 typedef enum {
545 
549 typedef struct {
559  uint32_t clkdiv1;
571  uint32_t rtc_clc;
585  uint32_t osc32ksel;
591  unsigned int clock_flags;
597  kinetis_mcg_mode_t default_mode;
614  uint8_t osc_clc;
624  uint8_t oscsel;
634  uint8_t fcrdiv;
644  uint8_t fll_frdiv;
659 #if KINETIS_HAVE_PLL
660 
669  uint8_t pll_prdiv;
679  uint8_t pll_vdiv;
680 #endif /* KINETIS_HAVE_PLL */
682 
689 void gpio_init_port(gpio_t pin, uint32_t pcr);
690 
691 #ifdef __cplusplus
692 }
693 #endif
694 
695 #endif /* PERIPH_CPU_H */
696 
uint8_t pll_prdiv
PLL ERC divider setting.
use alternate function 6
uint8_t osc_clc
OSC0 Capacitor Load Configuration bits.
fast mode: ~400kbit/s
enable pull-down
I2C configuration options.
emit interrupt on rising flank
FLL Bypassed External Mode.
IRQn_Type irqn
IRQ number for this module.
ADC resolution: 12 bit.
uint32_t base_freq
Input clock frequency.
CPU specific timer PIT module configuration.
use alternate function 4
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:99
Kinetis Low-power UART (LPUART) module type.
PLL Engaged External Mode.
use alternate function 5
kinetis_mcg_fll_t
Kinetis MCG FLL multiplier settings.
uint8_t src
Clock source setting.
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
enum IRQn IRQn_Type
Interrupt Number Definition.
SPI_Type * dev
SPI device to use.
kinetis_mcg_erc_range_t erc_range
ERC range setting.
gpio_pcr_t pcr
alternate pin function values
uint8_t irqn
IRQn interrupt number.
LPTMR_Type * dev
LPTMR device base pointer.
uint8_t oscsel
MCG external reference oscillator selection.
use pin as analog input
kinetis_clock_flags_t
Clock generation configuration flags.
uint8_t fcrdiv
Fast internal reference clock divider.
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
uint8_t chan
ADC channel.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
emit interrupt on both flanks
uart_mode_t
UART transmission modes.
FLL Bypassed Internal Mode.
Number of possible modes.
uint8_t pll_vdiv
PLL VCO divider setting.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
8 data bits, no parity, 1 stop bit
FLL Bypassed Low Power External Mode.
not supported by hardware
kinetis_mcg_erc_range_t
Kinetis FLL external reference clock range settings.
kinetis_mcg_fll_t fll_factor_fei
FLL multiplier when running in FEI mode.
ADC resolution: 10 bit.
uint32_t sda_pcr
PORT module PCR setting for the SDA pin.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Enable MCGIRCLK signal during STOP modes.
gpio_t adc_conf_t
ADC configuration wrapper.
uint32_t osc32ksel
ERCLK32K 32 kHz reference selection.
gpio_t pin_clk
CLK pin used.
use alternate function 2
uint32_t freq
I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.
not supported by hardware
use alternate function 7
FLL Engaged External Mode.
FLL Bypassed Low Power Internal Mode.
not supported by hardware
uint32_t scl_pcr
PORT module PCR setting for the SCL pin.
gpio_pcr_t
PORT control register bitmasks.
not supported by hardware
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
kinetis_mcg_mode
Kinetis possible MCG modes.
uart_mode_t mode
UART mode: data bits, parity, stop bits.
unsigned int clock_flags
Flags which will enable various clocking options at init.
Clock configuration for Kinetis CPUs.
for 31.25-39.0625 kHz crystal
I2C_Type * i2c
Pointer to hardware module registers.
Turn on OSC0 oscillator.
kinetis_mcg_mode_t default_mode
MCG mode used after initialization.
uint32_t pcr_tx
Pin configuration register bits for TX.
8 data bits, odd parity, 1 stop bit
UART device configuration.
use alternate function 3
input, no pull
IRQn_Type irqn
IRQ number for this module.
DAC line configuration data.
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
kinetis_mcg_fll_t fll_factor_fee
FLL multiplier when running in FEE mode.
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
uint32_t rtc_clc
RTC oscillator Capacitor Load Configuration bits.
uint32_t pcr_rx
Pin configuration register bits for RX.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
not supported
uart_type_t
UART hardware module types.
enum kinetis_mcg_mode kinetis_mcg_mode_t
Kinetis possible MCG modes.
FLL Engaged Internal Mode.
SPI module configuration options.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
PLL Bypassed External Mode.
normal mode: ~100kbit/s
CPU specific timer LPTMR module configuration.
input, pull-down
8 data bits, even parity, 1 stop bit
uint8_t fll_frdiv
FLL ERC divider setting.
Enable MCGIRCLK internal clock signal.
uint8_t scgc_bit
Clock enable bit, within the register.
Use the fast internal reference clock as MCGIRCLK signal.
ADC_Type * dev
ADC device.
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
Kinetis UART module type.
overall number of available ports
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.