kinetis/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2017-2018 Eistec AB
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 #define HAVE_GPIO_T
38 typedef uint16_t gpio_t;
44 #define GPIO_UNDEF (0xffff)
45 
49 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
50 
51 #ifdef SIM_UIDH_UID_MASK
52 /* Kinetis Cortex-M4 has a 128 bit SIM UID */
56 #define CPUID_ADDR (&SIM->UIDH)
57 
61 #define CPUID_LEN (16U)
62 #else /* defined(SIM_UIDH_UID_MASK) */
63 /* Kinetis Cortex-M0+ has a 96 bit SIM UID */
67 #define CPUID_ADDR (&SIM->UIDMH)
68 
71 #define CPUID_LEN (12U)
72 #endif /* defined(SIM_UIDH_UID_MASK) */
73 
83 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
84 
91 #define SPI_HWCS(x) (x)
92 
96 #define SPI_HWCS_NUMOF (5)
97 
102 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
103 #define PERIPH_SPI_NEEDS_TRANSFER_REG 1
104 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
105 
110 #define PERIPH_TIMER_PROVIDES_SET
111 
115 #define PM_NUM_MODES (1U)
116 
117 #ifndef DOXYGEN
118 
122 #define HAVE_GPIO_MODE_T
123 typedef enum {
124  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
125  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
126  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
127  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
128  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
129  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
130 } gpio_mode_t;
132 #endif /* ndef DOXYGEN */
133 
139 typedef enum {
140  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
141  GPIO_AF_GPIO = PORT_PCR_MUX(1),
142  GPIO_AF_2 = PORT_PCR_MUX(2),
143  GPIO_AF_3 = PORT_PCR_MUX(3),
144  GPIO_AF_4 = PORT_PCR_MUX(4),
145  GPIO_AF_5 = PORT_PCR_MUX(5),
146  GPIO_AF_6 = PORT_PCR_MUX(6),
147  GPIO_AF_7 = PORT_PCR_MUX(7),
148 #ifdef PORT_PCR_ODE_MASK
149  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
150 #endif
151  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
152  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
153 } gpio_pcr_t;
154 
155 #ifndef DOXYGEN
156 
160 #define HAVE_GPIO_FLANK_T
161 typedef enum {
162  GPIO_RISING = PORT_PCR_IRQC(0x9),
163  GPIO_FALLING = PORT_PCR_IRQC(0xa),
164  GPIO_BOTH = PORT_PCR_IRQC(0xb),
165 } gpio_flank_t;
167 #endif /* ndef DOXYGEN */
168 
174 enum {
175  PORT_A = 0,
176  PORT_B = 1,
177  PORT_C = 2,
178  PORT_D = 3,
179  PORT_E = 4,
180  PORT_F = 5,
181  PORT_G = 6,
183 };
184 
185 #ifndef DOXYGEN
186 
190 #define HAVE_ADC_RES_T
191 typedef enum {
192  ADC_RES_6BIT = (0xfe),
193  ADC_RES_8BIT = ADC_CFG1_MODE(0),
194  ADC_RES_10BIT = ADC_CFG1_MODE(2),
195  ADC_RES_12BIT = ADC_CFG1_MODE(1),
196  ADC_RES_14BIT = (0xff),
197  ADC_RES_16BIT = ADC_CFG1_MODE(3)
198 } adc_res_t;
201 #if defined(FTM_CnSC_MSB_MASK)
202 
205 #define PWM_CHAN_MAX (4U)
206 
211 #define HAVE_PWM_MODE_T
212 typedef enum {
213  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
214  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
215  PWM_CENTER = (FTM_CnSC_MSB_MASK)
216 } pwm_mode_t;
217 #endif /* defined(FTM_CnSC_MSB_MASK) */
218 #endif /* ndef DOXYGEN */
219 
223 typedef enum {
227 #if defined(UART_C1_M_MASK) || DOXYGEN
228  /* LPUART and UART mode bits coincide, so the same setting for UART works on
229  * the LPUART as well */
230  UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
231 #elif defined(LPUART_CTRL_M_MASK)
232  /* For CPUs which only have the LPUART */
233  UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
234 #endif
236 #if defined(UART_C1_M_MASK) || DOXYGEN
237  UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
238 #elif defined(LPUART_CTRL_M_MASK)
239  /* For CPUs which only have the LPUART */
240  UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
241 #endif
242 } uart_mode_t;
243 
244 #ifndef DOXYGEN
245 
249 #define HAVE_SPI_MODE_T
250 typedef enum {
251  SPI_MODE_0 = 0,
252  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
253  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
254  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
255 } spi_mode_t;
257 #endif /* ndef DOXYGEN */
258 
262 typedef struct {
263  ADC_Type *dev;
264  gpio_t pin;
266  uint8_t chan;
267 } adc_conf_t;
268 
269 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
270 
273 typedef struct {
274  DAC_Type *dev;
275  volatile uint32_t *scgc_addr;
276  uint8_t scgc_bit;
277 } dac_conf_t;
278 #endif
279 
283 typedef struct {
285  uint8_t prescaler_ch;
287  uint8_t count_ch;
288 } pit_conf_t;
289 
293 typedef struct {
295  LPTMR_Type *dev;
297  uint8_t irqn;
298 } lptmr_conf_t;
299 
300 #ifdef FTM_CnSC_MSB_MASK
301 
304 typedef struct {
305  FTM_Type* ftm;
306  struct {
307  gpio_t pin;
308  uint8_t af;
309  uint8_t ftm_chan;
310  } chan[PWM_CHAN_MAX];
311  uint8_t chan_numof;
312  uint8_t ftm_num;
313 } pwm_conf_t;
314 #endif
315 
319 typedef struct {
320  SPI_Type *dev;
321  gpio_t pin_miso;
322  gpio_t pin_mosi;
323  gpio_t pin_clk;
324  gpio_t pin_cs[SPI_HWCS_NUMOF];
326  uint32_t simmask;
327 } spi_conf_t;
328 
332 enum {
335 };
336 
342 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
343 
344 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
345 
350 typedef enum {
353 } uart_type_t;
354 
358 typedef struct {
359  void *dev;
360  uint32_t freq;
361  gpio_t pin_rx;
362  gpio_t pin_tx;
363  uint32_t pcr_rx;
364  uint32_t pcr_tx;
366  volatile uint32_t *scgc_addr;
367  uint8_t scgc_bit;
369  uart_type_t type;
370 } uart_conf_t;
371 
372 #if !defined(KINETIS_HAVE_PLL)
373 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
374 
377 #define KINETIS_HAVE_PLL 1
378 #else
379 #define KINETIS_HAVE_PLL 0
380 #endif
381 #endif /* !defined(KINETIS_HAVE_PLL) */
382 
386 typedef enum kinetis_mcg_mode {
393 #if KINETIS_HAVE_PLL
396 #endif
399 
403 typedef enum {
405  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
407  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
409  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
411  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
413  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
415  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
417  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
419  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
421 
425 typedef enum {
426  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
427  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
428  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
430 
437 typedef enum {
492 
496 typedef struct {
506  uint32_t clkdiv1;
518  uint32_t rtc_clc;
532  uint32_t osc32ksel;
538  unsigned int clock_flags;
544  kinetis_mcg_mode_t default_mode;
561  uint8_t osc_clc;
571  uint8_t oscsel;
581  uint8_t fcrdiv;
591  uint8_t fll_frdiv;
606 #if KINETIS_HAVE_PLL
607 
616  uint8_t pll_prdiv;
626  uint8_t pll_vdiv;
627 #endif /* KINETIS_HAVE_PLL */
629 
636 void gpio_init_port(gpio_t pin, uint32_t pcr);
637 
638 #ifdef __cplusplus
639 }
640 #endif
641 
642 #endif /* PERIPH_CPU_H */
643 
uint8_t pll_prdiv
PLL ERC divider setting.
use alternate function 6
uint8_t osc_clc
OSC0 Capacitor Load Configuration bits.
enable pull-down
emit interrupt on rising flank
FLL Bypassed External Mode.
IRQn_Type irqn
IRQ number for this module.
ADC resolution: 12 bit.
CPU specific timer PIT module configuration.
use alternate function 4
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:99
Kinetis Low-power UART (LPUART) module type.
PLL Engaged External Mode.
use alternate function 5
kinetis_mcg_fll_t
Kinetis MCG FLL multiplier settings.
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
enum IRQn IRQn_Type
Interrupt Number Definition.
SPI_Type * dev
SPI device to use.
kinetis_mcg_erc_range_t erc_range
ERC range setting.
gpio_pcr_t pcr
alternate pin function values
uint8_t irqn
IRQn interrupt number.
LPTMR_Type * dev
LPTMR device base pointer.
uint8_t oscsel
MCG external reference oscillator selection.
use pin as analog input
kinetis_clock_flags_t
Clock generation configuration flags.
uint8_t fcrdiv
Fast internal reference clock divider.
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
uint8_t chan
ADC channel.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
emit interrupt on both flanks
uart_mode_t
UART transmission modes.
FLL Bypassed Internal Mode.
Number of possible modes.
uint8_t pll_vdiv
PLL VCO divider setting.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
8 data bits, no parity, 1 stop bit
FLL Bypassed Low Power External Mode.
not supported by hardware
kinetis_mcg_erc_range_t
Kinetis FLL external reference clock range settings.
kinetis_mcg_fll_t fll_factor_fei
FLL multiplier when running in FEI mode.
ADC resolution: 10 bit.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Enable MCGIRCLK signal during STOP modes.
gpio_t adc_conf_t
ADC configuration wrapper.
uint32_t osc32ksel
ERCLK32K 32 kHz reference selection.
gpio_t pin_clk
CLK pin used.
use alternate function 2
not supported by hardware
use alternate function 7
FLL Engaged External Mode.
FLL Bypassed Low Power Internal Mode.
not supported by hardware
gpio_pcr_t
PORT control register bitmasks.
not supported by hardware
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
kinetis_mcg_mode
Kinetis possible MCG modes.
uart_mode_t mode
UART mode: data bits, parity, stop bits.
unsigned int clock_flags
Flags which will enable various clocking options at init.
Clock configuration for Kinetis CPUs.
for 31.25-39.0625 kHz crystal
Turn on OSC0 oscillator.
kinetis_mcg_mode_t default_mode
MCG mode used after initialization.
uint32_t pcr_tx
Pin configuration register bits for TX.
8 data bits, odd parity, 1 stop bit
UART device configuration.
use alternate function 3
input, no pull
DAC line configuration data.
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
kinetis_mcg_fll_t fll_factor_fee
FLL multiplier when running in FEE mode.
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
uint32_t rtc_clc
RTC oscillator Capacitor Load Configuration bits.
uint32_t pcr_rx
Pin configuration register bits for RX.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
not supported
uart_type_t
UART hardware module types.
enum kinetis_mcg_mode kinetis_mcg_mode_t
Kinetis possible MCG modes.
FLL Engaged Internal Mode.
SPI module configuration options.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
PLL Bypassed External Mode.
CPU specific timer LPTMR module configuration.
input, pull-down
8 data bits, even parity, 1 stop bit
uint8_t fll_frdiv
FLL ERC divider setting.
Enable MCGIRCLK internal clock signal.
uint8_t scgc_bit
Clock enable bit, within the register.
Use the fast internal reference clock as MCGIRCLK signal.
ADC_Type * dev
ADC device.
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
Kinetis UART module type.
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
overall number of available ports