kinetis/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include <stdint.h>
23 #include <stdbool.h>
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
35 #define HAVE_GPIO_T
36 typedef uint16_t gpio_t;
42 #define GPIO_UNDEF (0xffff)
43 
47 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
48 
52 #define CPUID_ADDR (&SIM->UIDH)
53 
56 #define CPUID_LEN (16U)
57 
67 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
68 
72 #define PWM_CHAN_MAX (4U)
73 
80 #define SPI_HWCS(x) (x)
81 
85 #define SPI_HWCS_NUMOF (5)
86 
91 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
92 #define PERIPH_SPI_NEEDS_TRANSFER_REG
93 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
94 
99 #define PERIPH_TIMER_PROVIDES_SET
100 
104 #define PM_NUM_MODES (1U)
105 
106 #ifndef DOXYGEN
107 
111 #define HAVE_GPIO_MODE_T
112 typedef enum {
113  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
114  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
115  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
116  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
117  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
118  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
119 } gpio_mode_t;
121 #endif /* ndef DOXYGEN */
122 
128 typedef enum {
129  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
130  GPIO_AF_GPIO = PORT_PCR_MUX(1),
131  GPIO_AF_2 = PORT_PCR_MUX(2),
132  GPIO_AF_3 = PORT_PCR_MUX(3),
133  GPIO_AF_4 = PORT_PCR_MUX(4),
134  GPIO_AF_5 = PORT_PCR_MUX(5),
135  GPIO_AF_6 = PORT_PCR_MUX(6),
136  GPIO_AF_7 = PORT_PCR_MUX(7),
137  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
138  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
139  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
140 } gpio_pcr_t;
141 
142 #ifndef DOXYGEN
143 
147 #define HAVE_GPIO_FLANK_T
148 typedef enum {
149  GPIO_RISING = PORT_PCR_IRQC(0x9),
150  GPIO_FALLING = PORT_PCR_IRQC(0xa),
151  GPIO_BOTH = PORT_PCR_IRQC(0xb),
152 } gpio_flank_t;
154 #endif /* ndef DOXYGEN */
155 
161 enum {
162  PORT_A = 0,
163  PORT_B = 1,
164  PORT_C = 2,
165  PORT_D = 3,
166  PORT_E = 4,
167  PORT_F = 5,
168  PORT_G = 6,
170 };
171 
172 #ifndef DOXYGEN
173 
177 #define HAVE_ADC_RES_T
178 typedef enum {
179  ADC_RES_6BIT = (0xfe),
180  ADC_RES_8BIT = ADC_CFG1_MODE(0),
181  ADC_RES_10BIT = ADC_CFG1_MODE(2),
182  ADC_RES_12BIT = ADC_CFG1_MODE(1),
183  ADC_RES_14BIT = (0xff),
184  ADC_RES_16BIT = ADC_CFG1_MODE(3)
185 } adc_res_t;
192 #define HAVE_PWM_MODE_T
193 typedef enum {
194  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
195  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
196  PWM_CENTER = (FTM_CnSC_MSB_MASK)
197 } pwm_mode_t;
199 #endif /* ndef DOXYGEN */
200 
204 typedef enum {
208 #if defined(UART_C1_M_MASK)
209  /* LPUART and UART mode bits coincide, so the same setting for UART works on
210  * the LPUART as well */
211  UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
212 #elif defined(LPUART_CTRL_M_MASK)
213  /* For CPUs which only have the LPUART */
214  UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
215 #endif
217 #if defined(UART_C1_M_MASK)
218  UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
219 #elif defined(LPUART_CTRL_M_MASK)
220  /* For CPUs which only have the LPUART */
221  UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
222 #endif
223 } uart_mode_t;
224 
225 #ifndef DOXYGEN
226 
230 #define HAVE_SPI_MODE_T
231 typedef enum {
232  SPI_MODE_0 = 0,
233  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
234  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
235  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
236 } spi_mode_t;
238 #endif /* ndef DOXYGEN */
239 
243 typedef struct {
244  ADC_Type *dev;
245  gpio_t pin;
247  uint8_t chan;
248 } adc_conf_t;
249 
250 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
251 
254 typedef struct {
255  DAC_Type *dev;
256  volatile uint32_t *scgc_addr;
257  uint8_t scgc_bit;
258 } dac_conf_t;
259 #endif
260 
264 typedef struct {
266  uint8_t prescaler_ch;
268  uint8_t count_ch;
269 } pit_conf_t;
270 
274 typedef struct {
276  LPTMR_Type *dev;
278  uint8_t irqn;
279 } lptmr_conf_t;
280 
284 typedef struct {
285  FTM_Type* ftm;
286  struct {
287  gpio_t pin;
288  uint8_t af;
289  uint8_t ftm_chan;
290  } chan[PWM_CHAN_MAX];
291  uint8_t chan_numof;
292  uint8_t ftm_num;
293 } pwm_conf_t;
294 
298 typedef struct {
299  SPI_Type *dev;
300  gpio_t pin_miso;
301  gpio_t pin_mosi;
302  gpio_t pin_clk;
303  gpio_t pin_cs[SPI_HWCS_NUMOF];
305  uint32_t simmask;
306 } spi_conf_t;
307 
311 enum {
314 };
315 
320 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
321 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
322 
327 typedef enum {
330 } uart_type_t;
331 
335 typedef struct {
336  void *dev;
337  uint32_t freq;
338  gpio_t pin_rx;
339  gpio_t pin_tx;
340  uint32_t pcr_rx;
341  uint32_t pcr_tx;
343  volatile uint32_t *scgc_addr;
344  uint8_t scgc_bit;
346  uart_type_t type;
347 } uart_conf_t;
348 
349 #if !defined(KINETIS_HAVE_PLL)
350 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
351 
354 #define KINETIS_HAVE_PLL 1
355 #else
356 #define KINETIS_HAVE_PLL 0
357 #endif
358 #endif /* !defined(KINETIS_HAVE_PLL) */
359 
363 typedef enum kinetis_mcg_mode {
370 #if KINETIS_HAVE_PLL
373 #endif
376 
380 typedef enum {
382  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
384  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
386  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
388  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
390  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
392  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
394  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
396  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
398 
402 typedef enum {
403  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
404  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
405  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
407 
411 typedef struct {
413  uint32_t clkdiv1;
415  kinetis_mcg_mode_t default_mode;
419  uint8_t fcrdiv;
421  uint8_t oscsel;
423  uint8_t clc;
425  uint8_t fll_frdiv;
430 #if KINETIS_HAVE_PLL
431 
432  uint8_t pll_prdiv;
434  uint8_t pll_vdiv;
435 #endif /* KINETIS_HAVE_PLL */
436 
454 
461 void gpio_init_port(gpio_t pin, uint32_t pcr);
462 
463 #ifdef __cplusplus
464 }
465 #endif
466 
467 #endif /* PERIPH_CPU_H */
468 
uint8_t pll_prdiv
PLL ERC divider setting, see reference manual for MCG_C5[PRDIV].
use alternate function 6
enable pull-down
uint8_t clc
Capacitor Load configuration bits, see reference manual for OSC_CR.
uint8_t ftm_num
FTM number used.
emit interrupt on rising flank
FLL Bypassed External Mode.
IRQn_Type irqn
IRQ number for this module.
FTM_Type * ftm
used FTM
ADC resolution: 12 bit.
CPU specific timer PIT module configuration.
use alternate function 4
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:99
Kinetis Low-power UART (LPUART) module type.
PLL Engaged External Mode.
use alternate function 5
kinetis_mcg_fll_t
Kinetis MCG FLL multiplier settings.
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
uint8_t af
alternate function mapping
enum IRQn IRQn_Type
Interrupt Number Definition.
bool enable_oscillator
External reference clock selection.
SPI_Type * dev
SPI device to use.
kinetis_mcg_erc_range_t erc_range
ERC range setting, see kinetis_mcg_erc_range_t.
gpio_pcr_t pcr
alternate pin function values
uint8_t irqn
IRQn interrupt number.
LPTMR_Type * dev
LPTMR device base pointer.
uint8_t oscsel
Oscillator selection, see reference manual for MCG_C7[OSCSEL].
use pin as analog input
uint8_t fcrdiv
Fast internal reference clock divider, see reference manual for MCG_SC[FCRDIV].
bool select_fast_irc
Use fast internal reference clock for MCGIRCLK.
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
uint8_t chan
ADC channel.
overall number of available ports
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
emit interrupt on both flanks
uint8_t chan_numof
number of actually configured channels
uart_mode_t
UART transmission modes.
FLL Bypassed Internal Mode.
Number of possible modes.
uint8_t pll_vdiv
PLL VCO divider setting, see reference manual for MCG_C6[VDIV0].
bool enable_mcgirclk
Enable MCGIRCLK output from MCG for use as alternate clock in some modules.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
8 data bits, no parity, 1 stop bit
FLL Bypassed Low Power External Mode.
not supported by hardware
kinetis_mcg_erc_range_t
Kinetis FLL external reference clock range settings.
kinetis_mcg_fll_t fll_factor_fei
FLL multiplier when running in FEI mode.
ADC resolution: 10 bit.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
gpio_t pin_clk
CLK pin used.
use alternate function 2
not supported by hardware
use alternate function 7
FLL Engaged External Mode.
FLL Bypassed Low Power Internal Mode.
not supported by hardware
gpio_pcr_t
Define a condensed set of PORT PCR values.
not supported by hardware
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
kinetis_mcg_mode
Kinetis possible MCG modes.
gpio_t pin
GPIO pin used, set to GPIO_UNDEF.
uart_mode_t mode
UART mode: data bits, parity, stop bits.
Clock configuration for Kinetis CPUs.
uint8_t ftm_chan
the actual FTM channel used
for 31.25-39.0625 kHz crystal
kinetis_mcg_mode_t default_mode
MCG mode used after initialization, see kinetis_mcg_mode_t.
uint32_t pcr_tx
Pin configuration register bits for TX.
UART device configuration.
use alternate function 3
input, no pull
DAC line configuration data.
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
kinetis_mcg_fll_t fll_factor_fee
FLL multiplier when running in FEE mode.
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
#define PWM_CHAN_MAX
Define the maximum number of PWM channels that can be configured.
uint32_t pcr_rx
Pin configuration register bits for RX.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
not supported
uart_type_t
UART hardware module types.
enum kinetis_mcg_mode kinetis_mcg_mode_t
Kinetis possible MCG modes.
FLL Engaged Internal Mode.
SPI module configuration options.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
PLL Bypassed External Mode.
CPU specific timer LPTMR module configuration.
input, pull-down
uint8_t fll_frdiv
FLL ERC divider setting, see reference manual for MCG_C1[FRDIV].
uint8_t scgc_bit
Clock enable bit, within the register.
ADC_Type * dev
ADC device.
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
Kinetis UART module type.
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.