stm32_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
37  defined(CPU_FAM_STM32L1)
38 #define CLOCK_LSI (37000U)
39 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
40  defined(CPU_FAM_STM32L4)
41 #define CLOCK_LSI (32000U)
42 #else
43 #error "error: LSI clock speed not defined for your target CPU"
44 #endif
45 
51 #define CPUID_LEN (12U)
52 
56 #define PROVIDES_PM_LAYERED_OFF
57 
61 #define TIMER_CHAN (4U)
62 
66 #define QDEC_CHAN (2U)
67 
72 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
73 #define PERIPH_SPI_NEEDS_TRANSFER_REG
74 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
75 
80 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
81  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0) || defined(DOXYGEN)
82 #define PM_NUM_MODES (2U)
83 
88 #define STM32_PM_STOP (1U)
89 #define STM32_PM_STANDBY (0U)
90 
91 #endif
92 
96 typedef enum {
97  APB1,
98  APB2,
99 #if defined(CPU_FAM_STM32L0)
100  AHB,
101  IOP,
102 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
103  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
104  AHB,
105 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
106  || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
107  AHB1,
108  AHB2,
109  AHB3
110 #else
111 #warning "unsupported stm32XX family"
112 #endif
113 } bus_t;
114 
115 #ifndef DOXYGEN
116 
120 #define HAVE_GPIO_T
121 typedef uint32_t gpio_t;
123 #endif
124 
128 #define GPIO_UNDEF (0xffffffff)
129 
133 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
134 
141 #define SPI_HWCS_MASK (0xffffff00)
142 
149 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
150 
156 #define PERIPH_I2C_NEED_READ_REG
157 
158 #define PERIPH_I2C_NEED_WRITE_REG
159 
164 typedef enum {
165 #ifdef CPU_FAM_STM32F1
166  GPIO_AF_OUT_PP = 0xb,
167  GPIO_AF_OUT_OD = 0xf,
168 #else
169  GPIO_AF0 = 0,
177 #ifndef CPU_FAM_STM32F0
186 #endif
187 #endif
188 } gpio_af_t;
189 
190 #ifndef CPU_FAM_STM32F1
191 
199 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
200 
201 #ifndef DOXYGEN
202 
206 #define HAVE_GPIO_MODE_T
207 typedef enum {
208  GPIO_IN = GPIO_MODE(0, 0, 0),
209  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
210  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
211  GPIO_OUT = GPIO_MODE(1, 0, 0),
212  GPIO_OD = GPIO_MODE(1, 0, 1),
213  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
214 } gpio_mode_t;
221 #define HAVE_GPIO_FLANK_T
222 typedef enum {
223  GPIO_RISING = 1,
224  GPIO_FALLING = 2,
225  GPIO_BOTH = 3
226 } gpio_flank_t;
228 #endif /* ndef DOXYGEN */
229 #endif /* ndef CPU_FAM_STM32F1 */
230 
231 #ifdef MODULE_PERIPH_DMA
232 
235 typedef struct {
236  int stream;
237 } dma_conf_t;
238 
242 typedef unsigned dma_t;
243 
247 typedef enum {
248  DMA_PERIPH_TO_MEM,
249  DMA_MEM_TO_PERIPH,
250  DMA_MEM_TO_MEM,
251 } dma_mode_t;
252 
257 #define DMA_INC_SRC_ADDR (0x01)
258 #define DMA_INC_DST_ADDR (0x02)
259 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
260 
266 #define DMA_DATA_WIDTH_BYTE (0x00)
267 #define DMA_DATA_WIDTH_HALF_WORD (0x04)
268 #define DMA_DATA_WIDTH_WORD (0x08)
269 #define DMA_DATA_WIDTH_MASK (0x0C)
270 #define DMA_DATA_WIDTH_SHIFT (2)
271 
272 #endif /* MODULE_PERIPH_DMA */
273 
277 typedef struct {
278  gpio_t pin;
279  uint8_t chan;
280 } dac_conf_t;
281 
285 typedef struct {
286  TIM_TypeDef *dev;
287  uint32_t max;
288  uint32_t rcc_mask;
289  uint8_t bus;
290  uint8_t irqn;
291 } timer_conf_t;
292 
296 typedef struct {
297  gpio_t pin;
298  uint8_t cc_chan;
299 } pwm_chan_t;
300 
304 typedef struct {
305  TIM_TypeDef *dev;
306  uint32_t rcc_mask;
309  gpio_af_t af;
310  uint8_t bus;
311 } pwm_conf_t;
312 
316 typedef struct {
317  gpio_t pin;
318  uint8_t cc_chan;
319 } qdec_chan_t;
320 
324 typedef struct {
325  TIM_TypeDef *dev;
326  uint32_t max;
327  uint32_t rcc_mask;
330  gpio_af_t af;
331  uint8_t bus;
332  uint8_t irqn;
333 } qdec_conf_t;
334 
338 typedef struct {
339  USART_TypeDef *dev;
340  uint32_t rcc_mask;
341  gpio_t rx_pin;
342  gpio_t tx_pin;
343 #ifndef CPU_FAM_STM32F1
344  gpio_af_t rx_af;
345  gpio_af_t tx_af;
346 #endif
347  uint8_t bus;
348  uint8_t irqn;
349 #ifdef MODULE_PERIPH_DMA
350  dma_t dma;
351  uint8_t dma_chan;
352 #endif
353 #ifdef MODULE_STM32_PERIPH_UART_HW_FC
354  gpio_t cts_pin;
355  gpio_t rts_pin;
356 #ifndef CPU_FAM_STM32F1
357  gpio_af_t cts_af;
358  gpio_af_t rts_af;
359 #endif
360 #endif
361 } uart_conf_t;
362 
366 typedef struct {
367  SPI_TypeDef *dev;
368  gpio_t mosi_pin;
369  gpio_t miso_pin;
370  gpio_t sclk_pin;
371  gpio_t cs_pin;
372 #ifndef CPU_FAM_STM32F1
373  gpio_af_t af;
374 #endif
375  uint32_t rccmask;
376  uint8_t apbbus;
377 #ifdef MODULE_PERIPH_DMA
378  dma_t tx_dma;
379  uint8_t tx_dma_chan;
380  dma_t rx_dma;
381  uint8_t rx_dma_chan;
382 #endif
383 } spi_conf_t;
384 
389 #define HAVE_I2C_SPEED_T
390 typedef enum {
391 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
392  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
393  I2C_SPEED_LOW,
394 #endif
397 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
398  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
399  defined(CPU_FAM_STM32L4)
401 #endif
402 } i2c_speed_t;
408 typedef struct {
409  I2C_TypeDef *dev;
410  i2c_speed_t speed;
411  gpio_t scl_pin;
412  gpio_t sda_pin;
413 #ifndef CPU_FAM_STM32F1
414  gpio_af_t scl_af;
415  gpio_af_t sda_af;
416 #endif
417  uint8_t bus;
418  uint32_t rcc_mask;
419 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
420  uint32_t rcc_sw_mask;
421 #endif
422 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
423  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
424  uint32_t clk;
425 #endif
426  uint8_t irqn;
427 } i2c_conf_t;
428 
429 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
430  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
431  defined(CPU_FAM_STM32L4)
432 
443 typedef struct {
444  uint8_t presc;
445  uint8_t scll;
446  uint8_t sclh;
447  uint8_t sdadel;
448  uint8_t scldel;
449 } i2c_timing_param_t;
450 #endif
451 
459 uint32_t periph_apb_clk(uint8_t bus);
460 
468 uint32_t periph_timer_clk(uint8_t bus);
469 
476 void periph_clk_en(bus_t bus, uint32_t mask);
477 
484 void periph_clk_dis(bus_t bus, uint32_t mask);
485 
492 void gpio_init_af(gpio_t pin, gpio_af_t af);
493 
499 void gpio_init_analog(gpio_t pin);
500 
501 #ifdef MODULE_PERIPH_DMA
502 
505 #define DMA_STREAM_UNDEF (UINT_MAX)
506 
510 void dma_init(void);
511 
528 int dma_transfer(dma_t dma, int chan, const void *src, void *dst, size_t len,
529  dma_mode_t mode, uint8_t flags);
530 
536 void dma_acquire(dma_t dma);
537 
543 void dma_release(dma_t dma);
544 
553 void dma_start(dma_t dma);
554 
562 uint16_t dma_suspend(dma_t dma);
563 
570 void dma_resume(dma_t dma, uint16_t remaining);
571 
577 void dma_stop(dma_t dma);
578 
584 void dma_wait(dma_t dma);
585 
599 int dma_configure(dma_t dma, int chan, const void *src, void *dst, size_t len,
600  dma_mode_t mode, uint8_t flags);
601 
611 static inline DMA_TypeDef *dma_base(int stream)
612 {
613  return (stream < 8) ? DMA1 : DMA2;
614 }
615 
621 static inline void dma_poweron(int stream)
622 {
623  if (stream < 8) {
624  periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
625  }
626  else {
627  periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
628  }
629 }
630 
638 static inline DMA_Stream_TypeDef *dma_stream(int stream)
639 {
640  uint32_t base = (uint32_t)dma_base(stream);
641 
642  return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
643 }
644 
652 static inline int dma_hl(int stream)
653 {
654  return ((stream & 0x4) >> 2);
655 }
656 
662 static inline uint32_t dma_ifc(int stream)
663 {
664  switch (stream & 0x3) {
665  case 0:
666  return (1 << 5);
667  case 1:
668  return (1 << 11);
669  case 2:
670  return (1 << 21);
671  case 3:
672  return (1 << 27);
673  default:
674  return 0;
675  }
676 }
677 
683 static inline void dma_isr_enable(int stream)
684 {
685  if (stream < 7) {
686  NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
687  }
688  else if (stream == 7) {
689  NVIC_EnableIRQ(DMA1_Stream7_IRQn);
690  }
691  else if (stream < 13) {
692  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
693  }
694  else if (stream < 16) {
695  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
696  }
697 }
698 
704 static inline void dma_isr_disable(int stream)
705 {
706  if (stream < 7) {
707  NVIC_DisableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
708  }
709  else if (stream == 7) {
710  NVIC_DisableIRQ(DMA1_Stream7_IRQn);
711  }
712  else if (stream < 13) {
713  NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
714  }
715  else if (stream < 16) {
716  NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
717  }
718 }
719 
725 static inline void dma_isr_clear(int stream)
726 {
727  if (stream < 7) {
728  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
729  }
730  else if (stream == 7) {
731  NVIC_ClearPendingIRQ((IRQn_Type)DMA1_Stream7_IRQn);
732  }
733  else if (stream < 13) {
734  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
735  }
736  else if (stream < 16) {
737  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
738  }
739 }
740 #endif /* MODULE_PERIPH_DMA */
741 
742 #ifdef __cplusplus
743 }
744 #endif
745 
746 #endif /* PERIPH_CPU_COMMON_H */
747 
use alternate function 4
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
use alternate function 7
I2C configuration options.
emit interrupt on rising flank
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
use alternate function 8
uint32_t rcc_mask
bit in clock enable register
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
use alternate function 10
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
gpio_t pin
pin connected to the line
use alternate function 6
use alternate function 14
uint32_t rcc_mask
bit in clock enable register
enum IRQn IRQn_Type
Interrupt Number Definition.
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
TIM_TypeDef * dev
Timer used.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
use alternate function 3
gpio_t pin
GPIO pin mapped to this channel.
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
gpio_af_t af
alternate function used
uint8_t irqn
global IRQ channel
use alternate function 1
gpio_af_t af
pin alternate function
emit interrupt on both flanks
uint32_t max
Maximum counter value.
use alternate function 0
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
gpio_af_t scl_af
scl pin alternate function value
use alternate function 5
use alternate function 11
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
gpio_af_t rx_af
alternate function for RX pin
input, no pull
TIM_TypeDef * dev
timer device
DAC line configuration data.
uint32_t rccmask
bit in the RCC peripheral enable register
uint8_t irqn
I2C event interrupt number.
not supported
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI module configuration options.
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
input, pull-down
gpio_af_t sda_af
sda pin alternate function value
gpio_af_t af
alternate function used
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
use alternate function 2
uint8_t cc_chan
capture compare channel used
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.