stm32_common/include/periph_cpu_common.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
37  defined(CPU_FAM_STM32L1)
38 #define CLOCK_LSI (37000U)
39 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
40  defined(CPU_FAM_STM32L4)
41 #define CLOCK_LSI (32000U)
42 #else
43 #error "error: LSI clock speed not defined for your target CPU"
44 #endif
45 
51 #define CPUID_LEN (12U)
52 
56 #define PROVIDES_PM_LAYERED_OFF
57 
61 #define TIMER_CHAN (4U)
62 
66 #define QDEC_CHAN (2U)
67 
72 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
73 #define PERIPH_SPI_NEEDS_TRANSFER_REG
74 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
75 
80 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
81  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0) || defined(DOXYGEN)
82 #define PM_NUM_MODES (2U)
83 
88 #define STM32_PM_STOP (1U)
89 #define STM32_PM_STANDBY (0U)
90 
91 #endif
92 
96 typedef enum {
97  APB1,
98  APB2,
99 #if defined(CPU_FAM_STM32L0)
100  AHB,
101  IOP,
102 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
103  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
104  AHB,
105 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
106  || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
107  AHB1,
108  AHB2,
109  AHB3
110 #else
111 #warning "unsupported stm32XX family"
112 #endif
113 } bus_t;
114 
115 #ifndef DOXYGEN
116 
120 #define HAVE_GPIO_T
121 typedef uint32_t gpio_t;
123 #endif
124 
128 #define GPIO_UNDEF (0xffffffff)
129 
133 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
134 
141 #define SPI_HWCS_MASK (0xffffff00)
142 
149 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
150 
154 typedef enum {
155 #ifdef CPU_FAM_STM32F1
156  GPIO_AF_OUT_PP = 0xb,
157  GPIO_AF_OUT_OD = 0xf,
158 #else
159  GPIO_AF0 = 0,
167 #ifndef CPU_FAM_STM32F0
176 #endif
177 #endif
178 } gpio_af_t;
179 
180 #ifndef CPU_FAM_STM32F1
181 
189 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
190 
191 #ifndef DOXYGEN
192 
196 #define HAVE_GPIO_MODE_T
197 typedef enum {
198  GPIO_IN = GPIO_MODE(0, 0, 0),
199  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
200  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
201  GPIO_OUT = GPIO_MODE(1, 0, 0),
202  GPIO_OD = GPIO_MODE(1, 0, 1),
203  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
204 } gpio_mode_t;
211 #define HAVE_GPIO_FLANK_T
212 typedef enum {
213  GPIO_RISING = 1,
214  GPIO_FALLING = 2,
215  GPIO_BOTH = 3
216 } gpio_flank_t;
218 #endif /* ndef DOXYGEN */
219 #endif /* ndef CPU_FAM_STM32F1 */
220 
221 #ifdef MODULE_PERIPH_DMA
222 
225 typedef struct {
226  int stream;
227 } dma_conf_t;
228 
232 typedef unsigned dma_t;
233 
237 typedef enum {
238  DMA_PERIPH_TO_MEM,
239  DMA_MEM_TO_PERIPH,
240  DMA_MEM_TO_MEM,
241 } dma_mode_t;
242 
247 #define DMA_INC_SRC_ADDR (0x01)
248 #define DMA_INC_DST_ADDR (0x02)
249 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
250 
256 #define DMA_DATA_WIDTH_BYTE (0x00)
257 #define DMA_DATA_WIDTH_HALF_WORD (0x04)
258 #define DMA_DATA_WIDTH_WORD (0x08)
259 #define DMA_DATA_WIDTH_MASK (0x0C)
260 #define DMA_DATA_WIDTH_SHIFT (2)
261 
262 #endif /* MODULE_PERIPH_DMA */
263 
267 typedef struct {
268  gpio_t pin;
269  uint8_t chan;
270 } dac_conf_t;
271 
275 typedef struct {
276  TIM_TypeDef *dev;
277  uint32_t max;
278  uint32_t rcc_mask;
279  uint8_t bus;
280  uint8_t irqn;
281 } timer_conf_t;
282 
286 typedef struct {
287  gpio_t pin;
288  uint8_t cc_chan;
289 } pwm_chan_t;
290 
294 typedef struct {
295  TIM_TypeDef *dev;
296  uint32_t rcc_mask;
299  gpio_af_t af;
300  uint8_t bus;
301 } pwm_conf_t;
302 
306 typedef struct {
307  gpio_t pin;
308  uint8_t cc_chan;
309 } qdec_chan_t;
310 
314 typedef struct {
315  TIM_TypeDef *dev;
316  uint32_t max;
317  uint32_t rcc_mask;
320  gpio_af_t af;
321  uint8_t bus;
322  uint8_t irqn;
323 } qdec_conf_t;
324 
328 typedef struct {
329  USART_TypeDef *dev;
330  uint32_t rcc_mask;
331  gpio_t rx_pin;
332  gpio_t tx_pin;
333 #ifndef CPU_FAM_STM32F1
334  gpio_af_t rx_af;
335  gpio_af_t tx_af;
336 #endif
337  uint8_t bus;
338  uint8_t irqn;
339 #ifdef MODULE_PERIPH_DMA
340  dma_t dma;
341  uint8_t dma_chan;
342 #endif
343 #ifdef MODULE_STM32_PERIPH_UART_HW_FC
344  gpio_t cts_pin;
345  gpio_t rts_pin;
346 #ifndef CPU_FAM_STM32F1
347  gpio_af_t cts_af;
348  gpio_af_t rts_af;
349 #endif
350 #endif
351 } uart_conf_t;
352 
356 typedef struct {
357  SPI_TypeDef *dev;
358  gpio_t mosi_pin;
359  gpio_t miso_pin;
360  gpio_t sclk_pin;
361  gpio_t cs_pin;
362 #ifndef CPU_FAM_STM32F1
363  gpio_af_t af;
364 #endif
365  uint32_t rccmask;
366  uint8_t apbbus;
367 #ifdef MODULE_PERIPH_DMA
368  dma_t tx_dma;
369  uint8_t tx_dma_chan;
370  dma_t rx_dma;
371  uint8_t rx_dma_chan;
372 #endif
373 } spi_conf_t;
374 
375 
383 uint32_t periph_apb_clk(uint8_t bus);
384 
392 uint32_t periph_timer_clk(uint8_t bus);
393 
400 void periph_clk_en(bus_t bus, uint32_t mask);
401 
408 void periph_clk_dis(bus_t bus, uint32_t mask);
409 
416 void gpio_init_af(gpio_t pin, gpio_af_t af);
417 
423 void gpio_init_analog(gpio_t pin);
424 
425 #ifdef MODULE_PERIPH_DMA
426 
429 #define DMA_STREAM_UNDEF (UINT_MAX)
430 
434 void dma_init(void);
435 
452 int dma_transfer(dma_t dma, int chan, const void *src, void *dst, size_t len,
453  dma_mode_t mode, uint8_t flags);
454 
460 void dma_acquire(dma_t dma);
461 
467 void dma_release(dma_t dma);
468 
477 void dma_start(dma_t dma);
478 
486 uint16_t dma_suspend(dma_t dma);
487 
494 void dma_resume(dma_t dma, uint16_t remaining);
495 
501 void dma_stop(dma_t dma);
502 
508 void dma_wait(dma_t dma);
509 
523 int dma_configure(dma_t dma, int chan, const void *src, void *dst, size_t len,
524  dma_mode_t mode, uint8_t flags);
525 
535 static inline DMA_TypeDef *dma_base(int stream)
536 {
537  return (stream < 8) ? DMA1 : DMA2;
538 }
539 
545 static inline void dma_poweron(int stream)
546 {
547  if (stream < 8) {
548  periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
549  }
550  else {
551  periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
552  }
553 }
554 
562 static inline DMA_Stream_TypeDef *dma_stream(int stream)
563 {
564  uint32_t base = (uint32_t)dma_base(stream);
565 
566  return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
567 }
568 
576 static inline int dma_hl(int stream)
577 {
578  return ((stream & 0x4) >> 2);
579 }
580 
586 static inline uint32_t dma_ifc(int stream)
587 {
588  switch (stream & 0x3) {
589  case 0:
590  return (1 << 5);
591  case 1:
592  return (1 << 11);
593  case 2:
594  return (1 << 21);
595  case 3:
596  return (1 << 27);
597  default:
598  return 0;
599  }
600 }
601 
607 static inline void dma_isr_enable(int stream)
608 {
609  if (stream < 7) {
610  NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
611  }
612  else if (stream == 7) {
613  NVIC_EnableIRQ(DMA1_Stream7_IRQn);
614  }
615  else if (stream < 13) {
616  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
617  }
618  else if (stream < 16) {
619  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
620  }
621 }
622 
628 static inline void dma_isr_disable(int stream)
629 {
630  if (stream < 7) {
631  NVIC_DisableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
632  }
633  else if (stream == 7) {
634  NVIC_DisableIRQ(DMA1_Stream7_IRQn);
635  }
636  else if (stream < 13) {
637  NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
638  }
639  else if (stream < 16) {
640  NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
641  }
642 }
643 
649 static inline void dma_isr_clear(int stream)
650 {
651  if (stream < 7) {
652  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
653  }
654  else if (stream == 7) {
655  NVIC_ClearPendingIRQ((IRQn_Type)DMA1_Stream7_IRQn);
656  }
657  else if (stream < 13) {
658  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
659  }
660  else if (stream < 16) {
661  NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
662  }
663 }
664 #endif /* MODULE_PERIPH_DMA */
665 
666 #ifdef __cplusplus
667 }
668 #endif
669 
670 #endif /* PERIPH_CPU_COMMON_H */
671 
use alternate function 4
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
use alternate function 7
emit interrupt on rising flank
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
use alternate function 8
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
use alternate function 10
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
gpio_t pin
pin connected to the line
use alternate function 6
use alternate function 14
uint32_t rcc_mask
bit in clock enable register
enum IRQn IRQn_Type
Interrupt Number Definition.
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
TIM_TypeDef * dev
Timer used.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
use alternate function 3
gpio_t pin
GPIO pin mapped to this channel.
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
gpio_af_t af
alternate function used
uint8_t irqn
global IRQ channel
use alternate function 1
PWM device configuration.
gpio_af_t af
pin alternate function
emit interrupt on both flanks
uint32_t max
Maximum counter value.
use alternate function 0
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
use alternate function 5
use alternate function 11
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
gpio_af_t rx_af
alternate function for RX pin
input, no pull
TIM_TypeDef * dev
timer device
DAC line configuration data.
uint32_t rccmask
bit in the RCC peripheral enable register
not supported
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI module configuration options.
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
input, pull-down
gpio_af_t af
alternate function used
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
use alternate function 2
uint8_t cc_chan
capture compare channel used
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.