periph_cpu.h File Reference

CPU specific definitions and functions for peripheral handling. More...

Detailed Description

CPU specific definitions and functions for peripheral handling.

Author
Gunar Schorcht gunar.nosp@m.@sch.nosp@m.orcht.nosp@m..net

Definition in file periph_cpu.h.

#include <stdint.h>
+ Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Data Structures

struct  i2c_conf_t
 I2C configuration options. More...
 
struct  spi_conf_t
 SPI configuration structure type. More...
 
struct  uart_conf_t
 UART device configuration. More...
 

Macros

#define CPUID_LEN   (7U)
 Length of the CPU_ID in octets.
 
#define ADC_NUMOF_MAX   16
 Number of ADC cahnnels that could be used at maximum. More...
 
#define PERIPH_I2C_NEED_READ_REG
 i2c_read_reg required
 
#define PERIPH_I2C_NEED_READ_REGS
 i2c_read_regs required
 
#define PERIPH_I2C_NEED_WRITE_REG
 i2c_write_reg required
 
#define PERIPH_I2C_NEED_WRITE_REGS
 i2c_write_regs required
 
#define PERIPH_TIMER_PROVIDES_SET
 Prevent shared timer functions from being used.
 

GPIO configuration

#define HAVE_GPIO_T
 Override the default gpio_t type definition. More...
 
typedef unsigned int gpio_t
 
#define GPIO_UNDEF   (0xffffffff)
 Definition of a fitting UNDEF value.
 
#define GPIO_PIN(x, y)   ((x & 0) | y)
 Define a CPU specific GPIO pin generator macro.
 
#define PORT_GPIO   (0)
 Available GPIO ports on ESP32.
 
#define GPIO_PIN_NUMOF   (40)
 Define CPU specific number of GPIO pins.
 
#define HAVE_GPIO_FLANK_T
 Override mode flank selection values.
 
enum  gpio_flank_t {
  GPIO_LOW, GPIO_BOTH, GPIO_FALLING, GPIO_RISING,
  GPIO_NONE = 0, GPIO_RISING = 1, GPIO_FALLING = 2, GPIO_BOTH = 3,
  GPIO_LOW = 4, GPIO_HIGH = 5, GPIO_FALLING = 0, GPIO_RISING = 1,
  GPIO_BOTH = 2
}
 
#define HAVE_GPIO_MODE_T
 Override GPIO modes.
 
enum  gpio_mode_t {
  GPIO_IN = ((uint8_t)OVERRIDE_DISABLE), GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG), GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN), GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP),
  GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE), GPIO_OD = (0xff), GPIO_OD_PU = (0xff), GPIO_IN,
  GPIO_IN_PD, GPIO_IN_PU, GPIO_OUT, GPIO_OD,
  GPIO_OD_PU, GPIO_IN_OUT, GPIO_IN_OD, GPIO_IN_OD_PU,
  GPIO_IN = (PIN_DIR_IN | PIN_MODE_NONE), GPIO_IN_PD = (PIN_DIR_IN | PIN_MODE_PD), GPIO_IN_PU = (PIN_DIR_IN | PIN_MODE_PU), GPIO_OUT = (PIN_DIR_OUT | PIN_MODE_NONE),
  GPIO_OD = (PIN_DIR_OUT | PIN_MODE_OD), GPIO_OD_PU = (PIN_DIR_OUT | PIN_MODE_OD | PIN_MODE_PU), GPIO_IN, GPIO_IN_PD,
  GPIO_IN_PU, GPIO_OUT, GPIO_OD, GPIO_OD_PU
}
 

Predefined GPIO names

#define GPIO0   (GPIO_PIN(PORT_GPIO,0))
 
#define GPIO1   (GPIO_PIN(PORT_GPIO,1))
 
#define GPIO2   (GPIO_PIN(PORT_GPIO,2))
 
#define GPIO3   (GPIO_PIN(PORT_GPIO,3))
 
#define GPIO4   (GPIO_PIN(PORT_GPIO,4))
 
#define GPIO5   (GPIO_PIN(PORT_GPIO,5))
 
#define GPIO6   (GPIO_PIN(PORT_GPIO,6))
 
#define GPIO7   (GPIO_PIN(PORT_GPIO,7))
 
#define GPIO8   (GPIO_PIN(PORT_GPIO,8))
 
#define GPIO9   (GPIO_PIN(PORT_GPIO,9))
 
#define GPIO10   (GPIO_PIN(PORT_GPIO,10))
 
#define GPIO11   (GPIO_PIN(PORT_GPIO,11))
 
#define GPIO12   (GPIO_PIN(PORT_GPIO,12))
 
#define GPIO13   (GPIO_PIN(PORT_GPIO,13))
 
#define GPIO14   (GPIO_PIN(PORT_GPIO,14))
 
#define GPIO15   (GPIO_PIN(PORT_GPIO,15))
 
#define GPIO16   (GPIO_PIN(PORT_GPIO,16))
 
#define GPIO17   (GPIO_PIN(PORT_GPIO,17))
 
#define GPIO18   (GPIO_PIN(PORT_GPIO,18))
 
#define GPIO19   (GPIO_PIN(PORT_GPIO,19))
 
#define GPIO21   (GPIO_PIN(PORT_GPIO,21))
 
#define GPIO22   (GPIO_PIN(PORT_GPIO,22))
 
#define GPIO23   (GPIO_PIN(PORT_GPIO,23))
 
#define GPIO25   (GPIO_PIN(PORT_GPIO,25))
 
#define GPIO26   (GPIO_PIN(PORT_GPIO,26))
 
#define GPIO27   (GPIO_PIN(PORT_GPIO,27))
 
#define GPIO32   (GPIO_PIN(PORT_GPIO,32))
 
#define GPIO33   (GPIO_PIN(PORT_GPIO,33))
 
#define GPIO34   (GPIO_PIN(PORT_GPIO,34))
 
#define GPIO35   (GPIO_PIN(PORT_GPIO,35))
 
#define GPIO36   (GPIO_PIN(PORT_GPIO,36))
 
#define GPIO37   (GPIO_PIN(PORT_GPIO,37))
 
#define GPIO38   (GPIO_PIN(PORT_GPIO,38))
 
#define GPIO39   (GPIO_PIN(PORT_GPIO,39))
 

ADC configuration

ESP32 integrates two 12-bit ADCs (ADC1 and ADC2) capable of measuring up to 18 analog signals in total.

Most of these ADC channels are either connected to a number of intergrated sensors like a Hall sensors, touch sensors and a temperature sensor or can be connected with certain GPIOs. Integrated sensors are disabled in RIOT's implementation and are not accessible. Thus, up to 18 GPIOs, the RTC GPIOs, can be used as ADC inputs:

  • ADC1 supports 8 channels: GPIO 32-39
  • ADC2 supports 10 channels: GPIO 0, 2, 4, 12-15, 25-27

For each ADC line, an attenuation of the input signal can be defined separately unsing function adc_set_attenuation, see file $RIOTBASE/cpu/esp32/include/adc_arch.h. This results in different full ranges of the measurable voltage at the input. The attenuation can be set to 0 dB, 3 dB, 6 dB and 11 dB, with 11 dB being the standard attenuation. Since an ADC input is measured against a reference voltage Vref of 1.1 V, approximately the following measurement ranges are given when using a corresponding attenuation:

Attenuation Voltage Range Symbol
0 dB 0 ... 1.1V (Vref) ADC_ATTENUATION_0_DB
3 dB 0 ... 1.5V ADC_ATTENUATION_3_DB
6 dB 0 ... 2.2V ADC_ATTENUATION_6_DB
11 dB (default) 0 ... 3.3V ADC_ATTENUATION_11_DB

Please note: The reference voltage Vref can vary from device to device in the range of 1.0V and 1.2V. The Vref of a device can be read with the function adc_vref_to_gpio25 at the pin GPIO 25, see file $RIOTBASE/cpu/esp32/include/adc_arch.h. The results of the ADC input can then be adjusted accordingly.

ADC_GPIOS in the board-specific peripheral configuration defines a list of GPIOs that can be used as ADC channels. The order of the listed GPIOs determines the mapping between the RIOT's ADC lines and the GPIOs.

Note
ADC_GPIOS must be defined even if there are no GPIOs that could be used as ADC channels on the board. In this case, an empy list hast to be defined which just contains the curly braces.

ADC_NUMOF is determined automatically from the ADC_GPIOS definition.

Note
As long as the GPIOs listed in ADC_GPIOS are not initialized as ADC channels with the adc_init function, they can be used for other purposes.
#define HAVE_ADC_RES_T
 Possible ADC resolution settings.
 
enum  adc_res_t {
  ADC_RES_6BIT = (0xa00), ADC_RES_7BIT = (0 << 4), ADC_RES_8BIT = (0xb00), ADC_RES_9BIT = (1 << 4),
  ADC_RES_10BIT = (2 << 4), ADC_RES_12BIT = (3 << 4), ADC_RES_14BIT = (0xc00), ADC_RES_16BIT = (0xd00),
  ADC_RES_6BIT = 0xf0, ADC_RES_8BIT = 0xf1, ADC_RES_9BIT = 0, ADC_RES_10BIT = 1,
  ADC_RES_11BIT = 2, ADC_RES_12BIT = 3, ADC_RES_14BIT = 0xf2, ADC_RES_16BIT = 0xf3,
  ADC_RES_6BIT = 0xf0, ADC_RES_8BIT = 0x00, ADC_RES_10BIT = 0x02, ADC_RES_12BIT = 0xf1,
  ADC_RES_14BIT = 0xf2, ADC_RES_16BIT = 0xf3, ADC_RES_6BIT = 0xf0, ADC_RES_8BIT = 0x00,
  ADC_RES_10BIT = 0x01, ADC_RES_12BIT = 0x02, ADC_RES_14BIT = 0xf1, ADC_RES_16BIT = 0xf2,
  ADC_RES_6BIT = 0x1, ADC_RES_8BIT = 0x2, ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10, ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
  ADC_RES_14BIT = 0x4, ADC_RES_16BIT = 0x8, ADC_RES_6BIT = 0xff, ADC_RES_8BIT = ADC_CTRLB_RESSEL_8BIT,
  ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT, ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT, ADC_RES_14BIT = 0xfe, ADC_RES_16BIT = 0xfd,
  ADC_RES_6BIT = 0xff, ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT, ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT, ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT,
  ADC_RES_14BIT = 0xfe, ADC_RES_16BIT = 0xfd, ADC_RES_6BIT = 0xff, ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT,
  ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT, ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT, ADC_RES_14BIT = 0xfe, ADC_RES_16BIT = 0xfd,
  ADC_RES_6BIT = 0x03000000, ADC_RES_8BIT = 0x02000000, ADC_RES_10BIT = 0x01000000, ADC_RES_12BIT = 0x00000000,
  ADC_RES_14BIT = 1, ADC_RES_16BIT = 2, ADC_RES_6BIT = (ADC_CR1_RES_0 | ADC_CR1_RES_1), ADC_RES_8BIT = (ADC_CR1_RES_1),
  ADC_RES_10BIT = (ADC_CR1_RES_0), ADC_RES_12BIT = (0x00), ADC_RES_14BIT = (0xfe), ADC_RES_16BIT = (0xff),
  ADC_RES_6BIT = 0, ADC_RES_8BIT, ADC_RES_10BIT, ADC_RES_12BIT,
  ADC_RES_14BIT, ADC_RES_16BIT
}
 

DAC configuration

ESP32 supports 2 DAC lines at GPIO25 and GPIO26.

These DACs have a width of 8 bits and produce voltages in the range from 0 V to 3.3 V (VDD_A). The 16 bits DAC values given as parameter of function dac_set are down-scaled to 8 bit.

DAC_GPIOS in the board-specific peripheral configuration defines a list of GPIOs that can be used as DAC channels. The order of the listed GPIOs determines the mapping between the RIOT's DAC lines and the GPIOs.

Note
DAC_GPIOS must be defined even if there are no GPIOs that could be used as DAC channels on the board. In this case, an empy list hast to be defined which just contains the curly braces.

DAC_NUMOF is determined automatically from the DAC_GPIOS definition.

Note
As long as the GPIOs listed in DAC_GPIOS are not initialized as DAC channels with the dac_init function, they can be used for other purposes.
#define DAC_NUMOF_MAX   2
 Number of DAC cahnnels that could be used at maximum.
 

I2C configuration

ESP32 has two built-in I2C interfaces.

The board-specific configuration of the I2C interface I2C_DEV(n) requires the defintion of

I2Cn_SPEED, the bus speed, I2Cn_SCL, the GPIO used as SCL signal, and I2Cn_SDA, the GPIO used as SDA signal,

where n can be 0 or 1. If they are not defined, the I2C interface I2C_DEV(n) is not used.

Note
The configuration of the I2C interfaces I2C_DEV(n) must be in continuous ascending order of n.

I2C_NUMOF is determined automatically from board-specific peripheral definitions of I2Cn_SPEED, I2Cn_SCK, and I2Cn_SDA.

#define HAVE_I2C_SPEED_T
 Override I2C clock speed values. More...
 
enum  i2c_speed_t {
  I2C_SPEED_LOW = 0x01, I2C_SPEED_NORMAL = 100000U, I2C_SPEED_FAST = 400000U, I2C_SPEED_FAST_PLUS = 0x02,
  I2C_SPEED_HIGH = 0x03, I2C_SPEED_LOW = 0, I2C_SPEED_NORMAL, I2C_SPEED_FAST,
  I2C_SPEED_FAST_PLUS, I2C_SPEED_HIGH, I2C_SPEED_LOW = 0x01, I2C_SPEED_NORMAL = TWI_FREQUENCY_FREQUENCY_K100,
  I2C_SPEED_FAST = TWI_FREQUENCY_FREQUENCY_K400, I2C_SPEED_FAST_PLUS = 0x02, I2C_SPEED_HIGH = 0x03, I2C_SPEED_LOW = 0xff,
  I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100, I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400, I2C_SPEED_FAST_PLUS = 0xfe, I2C_SPEED_HIGH = 0xfd,
  I2C_SPEED_LOW = 10000U, I2C_SPEED_NORMAL = 100000U, I2C_SPEED_FAST = 400000U, I2C_SPEED_FAST_PLUS = 1000000U,
  I2C_SPEED_HIGH = 3400000U, I2C_SPEED_NORMAL, I2C_SPEED_FAST, I2C_SPEED_LOW = 0,
  I2C_SPEED_NORMAL, I2C_SPEED_FAST, I2C_SPEED_FAST_PLUS, I2C_SPEED_HIGH
}
 

PWM configuration

PWM implementation uses ESP32's high-speed MCPWM modules.

ESP32 has 2 such modules, each with up to 6 channels (PWM_CHANNEL_NUM_DEV_MAX). Thus, the maximum number of PWM devices is 2 and the maximum total number of PWM channels is 12.

PWM0_GPIOS and PWM1_GPIOS in the board-specific peripheral configuration each define a list of GPIOs that can be used with the respective PWM devices as PWM channels. The order of the listed GPIOs determines the association between the RIOT PWM channels and the GPIOs.

Note
The definition of PWM0_GPIOS and PWM1_GPIOS can be omitted or empty. In the latter case, they must at least contain the curly braces. The corresponding PWM device can not be used in this case.

PWM_NUMOF is determined automatically from the PWM0_GPIOS and PWM1_GPIOS definitions.

Note
As long as the GPIOs listed in PWM0_GPIOS and PMW1_GPIOS are not initialized as PWM channels with the pwm_init function, they can be used other purposes.
#define PWM_NUMOF_MAX   (2)
 Maximum number of PWM devices.
 
#define PWM_CHANNEL_NUM_DEV_MAX   (6)
 Maximum number of channels per PWM device.
 

SPI configuration

ESP32 has four SPI controllers:

  • controller SPI0 is reserved for caching the flash memory (CPSI)
  • controller SPI1 is reserved for external memories like flash and PSRAM (FSPI)
  • controller SPI2 realizes interface HSPI that can be used for peripherals
  • controller SPI3 realizes interface VSPI that can be used for peripherals

Thus, a maximum of two SPI controllers can be used as peripheral interfaces:

  • VSPI
  • HSPI

SPI interfaces could be used in quad SPI mode, but RIOT's low level device driver doesn't support it.

The board-specific configuration of the SPI interface SPI_DEV(n) requires the defintion of

  • SPIn_CTRL, the SPI controller which is used for the interface (VSPI or HSPI),
  • SPIn_SCK, the GPIO used as clock signal
  • SPIn_MISO, the GPIO used as MISO signal
  • SPIn_MOSI, the GPIO used as MOSI signal, and
  • SPIn_CS0, the GPIO used as CS signal when the cs parameter in spi_aquire is GPIO_UNDEF,

where n can be 0 or 1. If they are not defined, the according SPI interface SPI_DEV(n) is not used.

SPI_NUMOF is determined automatically from the board-specific peripheral definitions of SPIn_*.

#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 requires function spi_transfer_byte
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
 requires function spi_transfer_reg
 
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 requires function spi_transfer_regs
 
enum  spi_ctrl_t { HSPI = 2, VSPI = 3 }
 SPI controllers that can be used for peripheral interfaces. More...
 

Timer configuration depenend on which implementation is used

Timers are MCU built-in feature and not board-specific.

They are therefore configured here.

#define TIMER_NUMOF   (3)
 hardware timer modules are used for timer implementation (default)
 
#define TIMER_CHANNELS   (1)
 
#define TIMER_SYSTEM   TIMERG0.hw_timer[0]
 Timer used for system time.
 

Macro Definition Documentation

◆ ADC_NUMOF_MAX

#define ADC_NUMOF_MAX   16

Number of ADC cahnnels that could be used at maximum.

Note
GPIO37 and GPIO38 are usually not broken out on ESP32 modules and are therefore not usable. The maximum number of ADC channels (ADC_NUMOF_MAX) is therefore set to 16.

Definition at line 244 of file periph_cpu.h.

◆ HAVE_GPIO_T

#define HAVE_GPIO_T

Override the default gpio_t type definition.

This is required here to have gpio_t defined in this file.

Definition at line 53 of file periph_cpu.h.

◆ HAVE_I2C_SPEED_T

#define HAVE_I2C_SPEED_T

Override I2C clock speed values.

This is required here to have i2c_speed_t defined in this file.

Definition at line 309 of file periph_cpu.h.

Enumeration Type Documentation

◆ adc_res_t

enum adc_res_t
Enumerator
ADC_RES_6BIT 

not supported by hardware

ADC_RES_7BIT 

ADC resolution: 7 bit.

ADC_RES_8BIT 

not supported by hardware

ADC_RES_9BIT 

ADC resolution: 9 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported by hardware

ADC_RES_16BIT 

not supported by hardware

ADC_RES_6BIT 

ADC resolution: 6 bit is not supported.

ADC_RES_8BIT 

ADC resolution: 8 bit is not supported.

ADC_RES_9BIT 

ADC resolution: 9 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_11BIT 

ADC resolution: 11 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

ADC resolution: 14 bit is not supported.

ADC_RES_16BIT 

ADC resolution: 16 bit is not supported.

ADC_RES_6BIT 

ADC resolution: 6 bit (not supported)

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit (not supported)

ADC_RES_14BIT 

ADC resolution: 14 bit (not supported)

ADC_RES_16BIT 

ADC resolution: 16 bit (not supported)

ADC_RES_6BIT 

not supported by hardware

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

supported with oversampling, not implemented

ADC_RES_16BIT 

not supported by hardware

ADC_RES_6BIT 

not applicable

ADC_RES_8BIT 

not applicable

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not applicable

ADC_RES_16BIT 

not applicable

ADC_RES_6BIT 

not supported

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported

ADC_RES_16BIT 

not supported

ADC_RES_6BIT 

not supported

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported

ADC_RES_16BIT 

not supported

ADC_RES_6BIT 

not supported

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported

ADC_RES_16BIT 

not supported

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

ADC resolution: 14 bit (not supported)

ADC_RES_16BIT 

ADC resolution: 16 bit (not supported)

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not applicable

ADC_RES_16BIT 

not applicable

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

ADC resolution: 14 bit.

ADC_RES_16BIT 

ADC resolution: 16 bit.

Definition at line 225 of file periph_cpu.h.

◆ gpio_flank_t

Enumerator
GPIO_LOW 

emit interrupt when pin low

GPIO_BOTH 

emit interrupt on both flanks

GPIO_FALLING 

emit interrupt on falling flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_FALLING 

emit interrupt on falling flank

GPIO_BOTH 

emit interrupt on both flanks

GPIO_LOW 

emit interrupt on low level

GPIO_HIGH 

emit interrupt on low level

GPIO_FALLING 

emit interrupt on falling flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_BOTH 

emit interrupt on both flanks

Definition at line 91 of file periph_cpu.h.

◆ gpio_mode_t

Enumerator
GPIO_IN 

input, no pull

GPIO_IN_ANALOG 

input, analog

GPIO_IN_PD 

input, pull-down

GPIO_IN_PU 

input, pull-up

GPIO_OUT 

output

GPIO_OD 

not supported

GPIO_OD_PU 

not supported

GPIO_IN 

input

GPIO_IN_PD 

input with pull-down

GPIO_IN_PU 

input with pull-up

GPIO_OUT 

output

GPIO_OD 

open-drain output

GPIO_OD_PU 

open-drain output with pull-up

GPIO_IN_OUT 

input and output

GPIO_IN_OD 

input and open-drain output

GPIO_IN_OD_PU 

input and open-drain output

GPIO_IN 

in without pull-up/down

GPIO_IN_PD 

in with pull-down

GPIO_IN_PU 

in with pull-up

GPIO_OUT 

push-pull output

GPIO_OD 

open-drain output

GPIO_OD_PU 

open-drain output with pull-up

GPIO_IN 

configure as input without pull resistor

GPIO_IN_PD 

configure as input with pull-down resistor

GPIO_IN_PU 

configure as input with pull-up resistor

GPIO_OUT 

configure as output in push-pull mode

GPIO_OD 

configure as output in open-drain mode without pull resistor

GPIO_OD_PU 

configure as output in open-drain mode with pull resistor enabled

Definition at line 108 of file periph_cpu.h.

◆ i2c_speed_t

Enumerator
I2C_SPEED_LOW 

not supported

I2C_SPEED_NORMAL 

normal mode: ~100kbit/s

I2C_SPEED_FAST 

fast mode: ~400kbit/s

I2C_SPEED_FAST_PLUS 

not supported

I2C_SPEED_HIGH 

not supported

I2C_SPEED_LOW 

10 kbit/s

I2C_SPEED_NORMAL 

100 kbit/s

I2C_SPEED_FAST 

400 kbit/s

I2C_SPEED_FAST_PLUS 

1 Mbit/s

I2C_SPEED_HIGH 

not supported

I2C_SPEED_LOW 

not supported

I2C_SPEED_NORMAL 

100kbit/s

I2C_SPEED_FAST 

400kbit/s

I2C_SPEED_FAST_PLUS 

not supported

I2C_SPEED_HIGH 

not supported

I2C_SPEED_LOW 

not supported

I2C_SPEED_NORMAL 

100kbit/s

I2C_SPEED_FAST 

400kbit/s

I2C_SPEED_FAST_PLUS 

not supported

I2C_SPEED_HIGH 

not supported

I2C_SPEED_LOW 

low speed mode: ~10kbit/s

I2C_SPEED_NORMAL 

normal mode: ~100kbit/s

I2C_SPEED_FAST 

fast mode: ~400kbit/s

I2C_SPEED_FAST_PLUS 

fast plus mode: ~1Mbit/s

I2C_SPEED_HIGH 

high speed mode: ~3.4Mbit/s

I2C_SPEED_NORMAL 

normal mode: ~100kbit/s

I2C_SPEED_FAST 

fast mode: ~400kbit/s

I2C_SPEED_LOW 

low speed mode: ~10 kbit/s

I2C_SPEED_NORMAL 

normal mode: ~100 kbit/s

I2C_SPEED_FAST 

fast mode: ~400 kbit/s

I2C_SPEED_FAST_PLUS 

fast plus mode: ~1000 kbit/s

I2C_SPEED_HIGH 

high speed mode: ~3400 kbit/s

Definition at line 310 of file periph_cpu.h.

◆ spi_ctrl_t

enum spi_ctrl_t

SPI controllers that can be used for peripheral interfaces.

Enumerator
HSPI 

HSPI interface controller.

VSPI 

VSPI interface controller.

Definition at line 410 of file periph_cpu.h.